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Commit c6d0e3b4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable Kryo erp driver for Yupik"

parents caeff04a 373317c4

bindings/arm/msm/qcom,llcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Properties: 
	Value type: <string>

	Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"

	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"

	            or "qcom,yupik-llcc"

		    "qcom,llcc-v2" must be appended for V2 hardware.



- reg:

qcom/ipcc-test-yupik.dtsi

0 → 100644
+5 −0
Original line number Diff line number Diff line 
#include "ipcc-test.dtsi"



&soc {

	/delete-node/ ipcc-self-ping-slpi;

};

qcom/yupik.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -752,6 +752,31 @@ 
		};

	};



	qcom,chd {

		compatible = "qcom,core-hang-detect";

		label = "core";

		qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058

				0x18040058 0x18050058 0x18060058 0x18070058>;

		qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060

				0x18040060 0x18050060 0x18060060 0x18070060>;

	};



	kryo-erp {

		compatible = "arm,arm64-kryo-cpu-erp";

		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";

	};



	cache-controller@9200000 {

		compatible = "qcom,yupik-llcc","qcom,llcc-v2";

		reg = <0x9200000 0xd0000>, <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "qdss_clk";

	};



	clk_virt: interconnect {

		compatible = "qcom,yupik-clk_virt";

		#interconnect-cells = <1>;
@@ -1160,6 +1185,7 @@ 
#include "yupik-pinctrl.dtsi"

#include "yupik-pm.dtsi"

#include "yupik-stub-regulator.dtsi"

#include "ipcc-test-yupik.dtsi"



&gcc_pcie_0_gdsc {

	compatible = "regulator-fixed";