Loading bindings/clock/qcom,camcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-camcc-v2" "qcom,sa8155-camcc" "qcom,sa8155-camcc-v2" "qcom,yupik-camcc" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in Loading bindings/clock/qcom,debugcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ Required properties : "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" "qcom,sm8150-debugcc" "qcom,yupik-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. Loading bindings/clock/qcom,dispcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ Required properties : "qcom,holi-dispcc" "qcom,sm8150-dispcc" "qcom,sm8150-dispcc-v2" "qcom,yupik-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. Loading bindings/clock/qcom,gcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -31,6 +31,7 @@ Required properties : "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" "qcom,yupik-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. Loading bindings/clock/qcom,gpucc.txt +6 −5 Original line number Diff line number Diff line Loading @@ -3,11 +3,12 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", "qcom,lahaina-gpucc", "qcom,shima-gpucc", "qcom,holi-gpucc", "qcom,sm8150-gpucc", "qcom,sa8155-gpucc". "qcom,lahaina-gpucc" "qcom,shima-gpucc" "qcom,holi-gpucc" "qcom,sm8150-gpucc" "qcom,sa8155-gpucc" "qcom,yupik-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Loading Loading
bindings/clock/qcom,camcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ Required properties : "qcom,sm8150-camcc-v2" "qcom,sa8155-camcc" "qcom,sa8155-camcc-v2" "qcom,yupik-camcc" - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in Loading
bindings/clock/qcom,debugcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ Required properties : "qcom,holi-debugcc" "qcom,sdxlemur-debugcc" "qcom,sm8150-debugcc" "qcom,yupik-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. Loading
bindings/clock/qcom,dispcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ Required properties : "qcom,holi-dispcc" "qcom,sm8150-dispcc" "qcom,sm8150-dispcc-v2" "qcom,yupik-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. Loading
bindings/clock/qcom,gcc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -31,6 +31,7 @@ Required properties : "qcom,shima-gcc" "qcom,holi-gcc" "qcom,sdxlemur-gcc" "qcom,yupik-gcc" - reg : shall contain base register location and length - vdd_cx-supply: The vdd_cx logic rail supply. Loading
bindings/clock/qcom,gpucc.txt +6 −5 Original line number Diff line number Diff line Loading @@ -3,11 +3,12 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc", "qcom,lahaina-gpucc", "qcom,shima-gpucc", "qcom,holi-gpucc", "qcom,sm8150-gpucc", "qcom,sa8155-gpucc". "qcom,lahaina-gpucc" "qcom,shima-gpucc" "qcom,holi-gpucc" "qcom,sm8150-gpucc" "qcom,sa8155-gpucc" "qcom,yupik-gpucc" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. Loading
