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Commit c68f3e7b authored by Ram Prakash Gupta's avatar Ram Prakash Gupta Committed by Gerrit - the friendly Code Review server
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Revert "ARM: dts: msm: Add UFS ICE HW controlled clock for yupik" 

This reverts commit b9792030.
Dynamic clk gating requires to be disabled post Auto Hibernate
to avoid ice clk gating by dcg.

Change-Id: I7684ce7b6c314132616e4826d9d14cc438514e81
parent 155f39f4

qcom/yupik.dtsi

+0 −3
Original line number Diff line number Diff line
@@ -2895,7 +2895,6 @@ 
			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"core_clk_ice_hw_ctl",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",
@@ -2906,7 +2905,6 @@ 
			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
@@ -2917,7 +2915,6 @@ 
			<0 0>,

			<75000000 300000000>,

			<75000000 300000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,