Merge "msm: pcie: update RC MPS based on MPSS" (c519e104) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/pci/controller/pci-msm.c

+14 −1

Original line number	Diff line number	Diff line
		@@ -103,6 +103,7 @@
		#define PCIE20_ELBI_SYS_STTS (0x08)

		#define PCIE20_CAP (0x70)
		#define PCIE20_CAP_DEVCAP (PCIE20_CAP + 0x04)
		#define PCIE20_CAP_DEVCTRLSTATUS (PCIE20_CAP + 0x08)
		#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
		#define PCIE_CAP_DLL_ACTIVE BIT(29)
		@@ -3646,6 +3647,8 @@ static void msm_pcie_config_aspm(struct msm_pcie_dev_t *pcie_dev)

		static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
		{
		u32 val;

		PCIE_DBG(dev, "RC%d\n", dev->rc_idx);

		/*
		@@ -3681,6 +3684,13 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
		PCIE20_DEVICE_CONTROL2_STATUS2,
		0xf, dev->cpl_timeout);

		/* update RC Max Payload Size based on Max Payload Size Supported */
		val = readl_relaxed(dev->dm_core + PCIE20_CAP_DEVCAP) &
		PCI_EXP_DEVCAP_PAYLOAD;
		msm_pcie_write_reg_field(dev->dm_core,
		PCIE20_CAP_DEVCTRLSTATUS,
		PCI_EXP_DEVCTL_PAYLOAD, val);

		/* Enable AER on RC */
		if (dev->aer_enable) {
		msm_pcie_write_mask(dev->dm_core + PCIE20_BRIDGE_CTRL, 0,
		@@ -4848,7 +4858,7 @@ int msm_pcie_enumerate(u32 rc_idx)
		struct pci_dev *pcidev = NULL;
		struct pci_host_bridge *bridge;
		bool found = false;
		struct pci_bus *bus;
		struct pci_bus bus, child;
		resource_size_t iobase = 0;
		u32 ids, vendor_id, device_id;
		LIST_HEAD(res);
		@@ -4930,6 +4940,9 @@ int msm_pcie_enumerate(u32 rc_idx)
		bus = bridge->bus;

		pci_assign_unassigned_bus_resources(bus);
		list_for_each_entry(child, &bus->children, node)
		pcie_bus_configure_settings(child);

		pci_bus_add_devices(bus);

		dev->enumerated = true;