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Commit 52eb9e14 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: update RC MPS based on MPSS 



Scale PCIe RC Max Payload Size (MPS) based on its capability
Max Payload Size Supported (MPSS). Configurating RC MPS to the
largest setting possible will help improve overall PCIe link
bandwidth performance.

Change-Id: Ice31cf0ab97fd7dd83736eea77e42ff00fb3148c
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent b96fd565

drivers/pci/controller/pci-msm.c

+10 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ 
#define PCIE20_ELBI_SYS_STTS (0x08)



#define PCIE20_CAP (0x70)

#define PCIE20_CAP_DEVCAP (PCIE20_CAP + 0x04)

#define PCIE20_CAP_DEVCTRLSTATUS (PCIE20_CAP + 0x08)

#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)

#define PCIE_CAP_DLL_ACTIVE BIT(29)
@@ -3646,6 +3647,8 @@ static void msm_pcie_config_aspm(struct msm_pcie_dev_t *pcie_dev) 


static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)

{

	u32 val;



	PCIE_DBG(dev, "RC%d\n", dev->rc_idx);



	/*
@@ -3681,6 +3684,13 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) 
					PCIE20_DEVICE_CONTROL2_STATUS2,

					0xf, dev->cpl_timeout);



	/* update RC Max Payload Size based on Max Payload Size Supported */

	val = readl_relaxed(dev->dm_core + PCIE20_CAP_DEVCAP) &

	      PCI_EXP_DEVCAP_PAYLOAD;

	msm_pcie_write_reg_field(dev->dm_core,

				 PCIE20_CAP_DEVCTRLSTATUS,

				 PCI_EXP_DEVCTL_PAYLOAD, val);



	/* Enable AER on RC */

	if (dev->aer_enable) {

		msm_pcie_write_mask(dev->dm_core + PCIE20_BRIDGE_CTRL, 0,