Merge branch 'core/urgent' into x86/fpu, to merge fixes (c29c7166) · Commits · e / devices / android_kernel_fairphone_FP5

CREDITS

+3 −2

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		@@ -1864,10 +1864,11 @@ S: The Netherlands

		N: Martin Kepplinger
		E: martink@posteo.de
		E: martin.kepplinger@theobroma-systems.com
		E: martin.kepplinger@ginzinger.com
		W: http://www.martinkepplinger.com
		D: mma8452 accelerators iio driver
		D: Kernel cleanups
		D: pegasus_notetaker input driver
		D: Kernel fixes and cleanups
		S: Garnisonstraße 26
		S: 4020 Linz
		S: Austria

+5 −2

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		@@ -220,8 +220,11 @@ What: /sys/class/cxl/<card>/reset
		Date: October 2014
		Contact: linuxppc-dev@lists.ozlabs.org
		Description: write only
		Writing 1 will issue a PERST to card which may cause the card
		to reload the FPGA depending on load_image_on_perst.
		Writing 1 will issue a PERST to card provided there are no
		contexts active on any one of the card AFUs. This may cause
		the card to reload the FPGA depending on load_image_on_perst.
		Writing -1 will do a force PERST irrespective of any active
		contexts on the card AFUs.
		Users: https://github.com/ibm-capi/libcxl

		What: /sys/class/cxl/<card>/perst_reloads_same_image (not in a guest)

+1 −0

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		@@ -309,3 +309,4 @@ Version History
		with a reshape in progress.
		1.9.0 Add support for RAID level takeover/reshape/region size
		and set size reduction.
		1.9.1 Fix activation of existing RAID 4/10 mapped devices

+8 −8

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		@@ -24,7 +24,7 @@ Example:
		reg = <0x61840000 0x4000>;

		clock {
		compatible = "socionext,uniphier-ld20-clock";
		compatible = "socionext,uniphier-ld11-clock";
		#clock-cells = <1>;
		};

		@@ -43,8 +43,8 @@ Provided clocks:
		21: USB3 ch1 PHY1


		Media I/O (MIO) clock
		---------------------
		Media I/O (MIO) clock, SD clock
		-------------------------------

		Required properties:
		- compatible: should be one of the following:
		@@ -52,10 +52,10 @@ Required properties:
		"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
		"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
		"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
		"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
		"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
		"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
		"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
		"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
		"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
		"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
		- #clock-cells: should be 1.

		Example:
		@@ -66,7 +66,7 @@ Example:
		reg = <0x59810000 0x800>;

		clock {
		compatible = "socionext,uniphier-ld20-mio-clock";
		compatible = "socionext,uniphier-ld11-mio-clock";
		#clock-cells = <1>;
		};

		@@ -112,7 +112,7 @@ Example:
		reg = <0x59820000 0x200>;

		clock {
		compatible = "socionext,uniphier-ld20-peri-clock";
		compatible = "socionext,uniphier-ld11-peri-clock";
		#clock-cells = <1>;
		};

0 → 100644

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		* Aspeed BT (Block Transfer) IPMI interface

		The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
		(BaseBoard Management Controllers) and the BT interface can be used to
		perform in-band IPMI communication with their host.

		Required properties:

		- compatible : should be "aspeed,ast2400-bt-bmc"
		- reg: physical address and size of the registers

		Optional properties:

		- interrupts: interrupt generated by the BT interface. without an
		interrupt, the driver will operate in poll mode.

		Example:

		ibt@1e789140 {
		compatible = "aspeed,ast2400-bt-bmc";
		reg = <0x1e789140 0x18>;
		interrupts = <8>;
		};