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Commit c21cd4ae authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels 



Correct the DMA channels for SCIF5 from 16..47 to 0..15, as was done for
R-Car E3.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 2660a6af ("arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent e20119f7

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+3 −4
Original line number Original line Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

/*

 * Device Tree Source for the RZ/G2E (R8A774C0) SoC

 * Device Tree Source for the RZ/G2E (R8A774C0) SoC

 *

 *

 * Copyright (C) 2018 Renesas Electronics Corp.

 * Copyright (C) 2018-2019 Renesas Electronics Corp.

 */

 */





#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>

#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
@@ -990,9 +990,8 @@ 
				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,

			dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;

			       <&dmac2 0x5b>, <&dmac2 0x5a>;

			dma-names = "tx", "rx";

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 202>;

			resets = <&cpg 202>;

			status = "disabled";

			status = "disabled";