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Commit 2660a6af authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes 



Add the device nodes for all RZ/G2E SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent e2088cf8

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+171 −0
Original line number Diff line number Diff line
@@ -126,6 +126,94 @@ 
			#power-domain-cells = <1>;

		};



		hscif0: serial@e6540000 {

			compatible = "renesas,hscif-r8a774c0",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6540000 0 0x60>;

			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 520>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x31>, <&dmac1 0x30>,

			       <&dmac2 0x31>, <&dmac2 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 520>;

			status = "disabled";

		};



		hscif1: serial@e6550000 {

			compatible = "renesas,hscif-r8a774c0",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6550000 0 0x60>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 519>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x33>, <&dmac1 0x32>,

			       <&dmac2 0x33>, <&dmac2 0x32>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 519>;

			status = "disabled";

		};



		hscif2: serial@e6560000 {

			compatible = "renesas,hscif-r8a774c0",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6560000 0 0x60>;

			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 518>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x35>, <&dmac1 0x34>,

			       <&dmac2 0x35>, <&dmac2 0x34>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 518>;

			status = "disabled";

		};



		hscif3: serial@e66a0000 {

			compatible = "renesas,hscif-r8a774c0",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe66a0000 0 0x60>;

			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 517>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x37>, <&dmac0 0x36>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 517>;

			status = "disabled";

		};



		hscif4: serial@e66b0000 {

			compatible = "renesas,hscif-r8a774c0",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe66b0000 0 0x60>;

			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 516>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x39>, <&dmac0 0x38>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 516>;

			status = "disabled";

		};



		dmac0: dma-controller@e6700000 {

			compatible = "renesas,dmac-r8a774c0",

				     "renesas,rcar-dmac";
@@ -228,6 +316,40 @@ 
			dma-channels = <16>;

		};



		scif0: serial@e6e60000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e60000 0 64>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 207>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,

			       <&dmac2 0x51>, <&dmac2 0x50>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 207>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 206>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,

			       <&dmac2 0x53>, <&dmac2 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 206>;

			status = "disabled";

		};



		scif2: serial@e6e88000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";
@@ -242,6 +364,55 @@ 
			status = "disabled";

		};



		scif3: serial@e6c50000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c50000 0 64>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 204>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x57>, <&dmac0 0x56>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 204>;

			status = "disabled";

		};



		scif4: serial@e6c40000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c40000 0 64>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 203>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x59>, <&dmac0 0x58>;

			dma-names = "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 203>;

			status = "disabled";

		};



		scif5: serial@e6f30000 {

			compatible = "renesas,scif-r8a774c0",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6f30000 0 64>;

			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 202>,

				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,

			       <&dmac2 0x5b>, <&dmac2 0x5a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 202>;

			status = "disabled";

		};



		gic: interrupt-controller@f1010000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;