Merge branch 'x86/tsc' into x86/core (be9a1d3c) · Commits · e / devices / android_kernel_fairphone_FP5

arch/x86/kernel/cpu/addon_cpuid_features.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -120,9 +120,17 @@ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
		c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
		& core_select_mask;
		c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
		/*
		* Reinit the apicid, now that we have extended initial_apicid.
		*/
		c->apicid = phys_pkg_id(c->initial_apicid, 0);
		#else
		c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
		c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
		/*
		* Reinit the apicid, now that we have extended initial_apicid.
		*/
		c->apicid = phys_pkg_id(0);
		#endif
		c->x86_max_cores = (core_level_siblings / smp_num_siblings);

+7 −2

Original line number	Diff line number	Diff line
		@@ -283,9 +283,14 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
		{
		early_init_amd_mc(c);

		/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
		if (c->x86_power & (1<<8))
		/*
		* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
		* with P/T states and does not stop in deep C-states
		*/
		if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
		}

		#ifdef CONFIG_X86_64
		set_cpu_cap(c, X86_FEATURE_SYSCALL32);

+17 −1

Original line number	Diff line number	Diff line
		@@ -41,6 +41,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
		if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
		#endif

		/*
		* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
		* with P/T states and does not stop in deep C-states
		*/
		if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
		}

		}

		#ifdef CONFIG_X86_32
		@@ -242,6 +252,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)

		intel_workarounds(c);

		/*
		* Detect the extended topology information if available. This
		* will reinitialise the initial_apicid which will be used
		* in init_intel_cacheinfo()
		*/
		detect_extended_topology(c);

		l2 = init_intel_cacheinfo(c);
		if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		@@ -312,7 +329,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
		if (cpu_has_bts)
		ptrace_bts_init_intel(c);

		detect_extended_topology(c);
		if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		* let's use the legacy cpuid vector 0x1 and 0x4 for topology

+1 −1

Original line number	Diff line number	Diff line
		@@ -287,7 +287,7 @@ static void c1e_idle(void)
		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
		c1e_detected = 1;
		if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
		if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
		mark_tsc_unstable("TSC halt in AMD C1E");
		printk(KERN_INFO "System has AMD C1E enabled\n");
		set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);

+3 −3

Original line number	Diff line number	Diff line
		@@ -374,15 +374,15 @@ static int tsc_halts_in_c(int state)
		{
		switch (boot_cpu_data.x86_vendor) {
		case X86_VENDOR_AMD:
		case X86_VENDOR_INTEL:
		/*
		* AMD Fam10h TSC will tick in all
		* C/P/S0/S1 states when this bit is set.
		*/
		if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
		if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
		return 0;

		/FALL THROUGH/
		case X86_VENDOR_INTEL:
		/* Several cases known where TSC halts in C2 too */
		default:
		return state > ACPI_STATE_C1;
		}