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Commit bdd22a41 authored by Baruch Siach's avatar Baruch Siach Committed by Gregory CLEMENT
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arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal 



The PHY reset signal goes to mpp43 on CP0.

Fixes: babc5544 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Reported-by: default avatarDenis Odintsov <oversun@me.com>
Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent 6fc97917

arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts

+1 −1
Original line number Diff line number Diff line
@@ -351,7 +351,7 @@ 
		reg = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&cp0_copper_eth_phy_reset>;

		reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;

		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;

		reset-assert-us = <10000>;

	};