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Commit babc5544 authored by Baruch Siach's avatar Baruch Siach Committed by Gregory CLEMENT
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arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal 



This reset signal controls the Marvell 1512 1G PHY.

Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.

Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent b597a6f5

arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts

+4 −0
Original line number Diff line number Diff line
@@ -333,6 +333,10 @@ 
		 */

		marvell,reg-init = <3 16 0 0x1017>;

		reg = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&cp0_copper_eth_phy_reset>;

		reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;

		reset-assert-us = <10000>;

	};



	switch0: switch0@4 {