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Commit bc84a2d1 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'kvm/cortex-a76-erratum-1165522' into aarch64/for-next/core 

Pull in KVM workaround for A76 erratum #116522.

Conflicts:
	arch/arm64/include/asm/cpucaps.h
parents f357b3a7 a457b0f7

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ stable kernels. 
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm/include/asm/kvm_host.h

+1 −1
Original line number Diff line number Diff line
@@ -285,7 +285,7 @@ void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 


struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);



static inline bool kvm_arch_check_sve_has_vhe(void) { return true; }

static inline bool kvm_arch_requires_vhe(void) { return false; }

static inline void kvm_arch_hardware_unsetup(void) {}

static inline void kvm_arch_sync_events(struct kvm *kvm) {}

static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}

arch/arm64/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -504,6 +504,18 @@ config ARM64_ERRATUM_1188873 


	  If unsure, say Y.



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	help

	  This option adds work arounds for ARM Cortex-A76 erratum 1165522



	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with

	  corrupted TLBs by speculating an AT instruction during a guest

	  context switch.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -55,7 +55,8 @@ 
#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1188873		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_1165522		37



#define ARM64_NCAPS				37

#define ARM64_NCAPS				38



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/kvm_host.h

+7 −3
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, 
	}

}



static inline bool kvm_arch_check_sve_has_vhe(void)

static inline bool kvm_arch_requires_vhe(void)

{

	/*

	 * The Arm architecture specifies that implementation of SVE
@@ -430,9 +430,13 @@ static inline bool kvm_arch_check_sve_has_vhe(void) 
	 * relies on this when SVE is present:

	 */

	if (system_supports_sve())

		return has_vhe();

	else

		return true;



	/* Some implementations have defects that confine them to VHE */

	if (cpus_have_cap(ARM64_WORKAROUND_1165522))

		return true;



	return false;

}



static inline void kvm_arch_hardware_unsetup(void) {}