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Commit a457b0f7 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
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arm64: Add configuration/documentation for Cortex-A76 erratum 1165522 



Now that the infrastructure to handle erratum 1165522 is in place,
let's make it a selectable option and add the required documentation.

Reviewed-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent eb036ad2

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ stable kernels. 
| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1188873        | ARM64_ERRATUM_1188873       |

| ARM            | Cortex-A76      | #1165522        | ARM64_ERRATUM_1165522       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -497,6 +497,18 @@ config ARM64_ERRATUM_1188873 


	  If unsure, say Y.



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	help

	  This option adds work arounds for ARM Cortex-A76 erratum 1165522



	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with

	  corrupted TLBs by speculating an AT instruction during a guest

	  context switch.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y