Loading qcom/lahaina-coresight.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -2433,6 +2433,7 @@ clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; status = "disabled"; qcom,msr-fix-req; out-ports { Loading Loading
qcom/lahaina-coresight.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -2433,6 +2433,7 @@ clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; status = "disabled"; qcom,msr-fix-req; out-ports { Loading