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Commit baba6e57 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: take a reference to uncore in the engine and use it 



A few advantages:

- Prepares us for the planned split of display uncore from GT uncore

- Improves our engine-centric view of the world in the engine code
  and allows us to avoid jumping back to dev_priv.

- Allows us to wrap accesses to engine register in nice macros that
  automatically pick the right mmio base.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-10-daniele.ceraolospurio@intel.com
parent 97a04e0d

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -1848,7 +1848,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);

	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);





	MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);

	MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);

	MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);

	MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);

	MMIO_D(GEN7_CXT_SIZE, D_ALL);

	MMIO_D(GEN7_CXT_SIZE, D_ALL);

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -880,7 +880,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
		for_each_engine(engine, dev_priv, id) {

		for_each_engine(engine, dev_priv, id) {

			seq_printf(m,

			seq_printf(m,

				   "Graphics Interrupt mask (%s):	%08x\n",

				   "Graphics Interrupt mask (%s):	%08x\n",

				   engine->name, I915_READ_IMR(engine));

				   engine->name, ENGINE_READ(engine, RING_IMR));

		}

		}

	}

	}

drivers/gpu/drm/i915/i915_gpu_error.c

+21 −21
Original line number Original line Diff line number Diff line
@@ -1136,7 +1136,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, 
	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *dev_priv = engine->i915;





	if (INTEL_GEN(dev_priv) >= 6) {

	if (INTEL_GEN(dev_priv) >= 6) {

		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));

		ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);

		if (INTEL_GEN(dev_priv) >= 8)

		if (INTEL_GEN(dev_priv) >= 8)

			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);

			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);

		else

		else
@@ -1144,32 +1144,32 @@ static void error_record_engine_registers(struct i915_gpu_state *error, 
	}

	}





	if (INTEL_GEN(dev_priv) >= 4) {

	if (INTEL_GEN(dev_priv) >= 4) {

		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));

		ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);

		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));

		ee->ipeir = ENGINE_READ(engine, RING_IPEIR);

		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));

		ee->ipehr = ENGINE_READ(engine, RING_IPEHR);

		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));

		ee->instps = ENGINE_READ(engine, RING_INSTPS);

		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));

		ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);

		if (INTEL_GEN(dev_priv) >= 8) {

		if (INTEL_GEN(dev_priv) >= 8) {

			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;

			ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;

			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;

			ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;

		}

		}

		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));

		ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);

	} else {

	} else {

		ee->faddr = I915_READ(DMA_FADD_I8XX);

		ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);

		ee->ipeir = I915_READ(IPEIR);

		ee->ipeir = ENGINE_READ(engine, IPEIR);

		ee->ipehr = I915_READ(IPEHR);

		ee->ipehr = ENGINE_READ(engine, IPEHR);

	}

	}





	intel_engine_get_instdone(engine, &ee->instdone);

	intel_engine_get_instdone(engine, &ee->instdone);





	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));

	ee->instpm = ENGINE_READ(engine, RING_INSTPM);

	ee->acthd = intel_engine_get_active_head(engine);

	ee->acthd = intel_engine_get_active_head(engine);

	ee->start = I915_READ_START(engine);

	ee->start = ENGINE_READ(engine, RING_START);

	ee->head = I915_READ_HEAD(engine);

	ee->head = ENGINE_READ(engine, RING_HEAD);

	ee->tail = I915_READ_TAIL(engine);

	ee->tail = ENGINE_READ(engine, RING_TAIL);

	ee->ctl = I915_READ_CTL(engine);

	ee->ctl = ENGINE_READ(engine, RING_CTL);

	if (INTEL_GEN(dev_priv) > 2)

	if (INTEL_GEN(dev_priv) > 2)

		ee->mode = I915_READ_MODE(engine);

		ee->mode = ENGINE_READ(engine, RING_MI_MODE);





	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {

	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {

		i915_reg_t mmio;

		i915_reg_t mmio;
@@ -1214,10 +1214,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, 




		if (IS_GEN(dev_priv, 6))

		if (IS_GEN(dev_priv, 6))

			ee->vm_info.pp_dir_base =

			ee->vm_info.pp_dir_base =

				I915_READ(RING_PP_DIR_BASE_READ(engine));

				ENGINE_READ(engine, RING_PP_DIR_BASE_READ);

		else if (IS_GEN(dev_priv, 7))

		else if (IS_GEN(dev_priv, 7))

			ee->vm_info.pp_dir_base =

			ee->vm_info.pp_dir_base =

				I915_READ(RING_PP_DIR_BASE(engine));

					ENGINE_READ(engine, RING_PP_DIR_BASE);

		else if (INTEL_GEN(dev_priv) >= 8)

		else if (INTEL_GEN(dev_priv) >= 8)

			for (i = 0; i < 4; i++) {

			for (i = 0; i < 4; i++) {

				ee->vm_info.pdp[i] =

				ee->vm_info.pdp[i] =
@@ -1601,7 +1601,7 @@ static void capture_reg_state(struct i915_gpu_state *error) 
	}

	}





	if (INTEL_GEN(dev_priv) >= 5)

	if (INTEL_GEN(dev_priv) >= 5)

		error->ccid = I915_READ(CCID);

		error->ccid = I915_READ(CCID(RENDER_RING_BASE));





	/* 3: Feature specific registers */

	/* 3: Feature specific registers */

	if (IS_GEN_RANGE(dev_priv, 6, 7)) {

	if (IS_GEN_RANGE(dev_priv, 6, 7)) {

drivers/gpu/drm/i915/i915_reg.h

+8 −8
Original line number Original line Diff line number Diff line
@@ -434,9 +434,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)

#define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)

#define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)

#define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)





#define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base + 0x228)

#define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)

#define RING_PP_DIR_BASE_READ(engine)	_MMIO((engine)->mmio_base + 0x518)

#define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)

#define RING_PP_DIR_DCLV(engine)	_MMIO((engine)->mmio_base + 0x220)

#define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)

#define   PP_DIR_DCLV_2G		0xffffffff

#define   PP_DIR_DCLV_2G		0xffffffff





#define GEN8_RING_PDP_UDW(engine, n)	_MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)

#define GEN8_RING_PDP_UDW(engine, n)	_MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
@@ -2568,12 +2568,12 @@ enum i915_power_well_id { 
#define HWS_START_ADDRESS_SHIFT	4

#define HWS_START_ADDRESS_SHIFT	4

#define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */

#define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */

#define   PWRCTX_EN	(1 << 0)

#define   PWRCTX_EN	(1 << 0)

#define IPEIR		_MMIO(0x2088)

#define IPEIR(base)	_MMIO((base) + 0x88)

#define IPEHR		_MMIO(0x208c)

#define IPEHR(base)	_MMIO((base) + 0x8c)

#define GEN2_INSTDONE	_MMIO(0x2090)

#define GEN2_INSTDONE	_MMIO(0x2090)

#define NOPID		_MMIO(0x2094)

#define NOPID		_MMIO(0x2094)

#define HWSTAM		_MMIO(0x2098)

#define HWSTAM		_MMIO(0x2098)

#define DMA_FADD_I8XX	_MMIO(0x20d0)

#define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)

#define RING_BBSTATE(base)	_MMIO((base) + 0x110)

#define RING_BBSTATE(base)	_MMIO((base) + 0x110)

#define   RING_BB_PPGTT		(1 << 5)

#define   RING_BB_PPGTT		(1 << 5)

#define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */

#define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
@@ -2747,7 +2747,7 @@ enum i915_power_well_id { 
#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */

#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */

#define   INSTPM_TLB_INVALIDATE	(1 << 9)

#define   INSTPM_TLB_INVALIDATE	(1 << 9)

#define   INSTPM_SYNC_FLUSH	(1 << 5)

#define   INSTPM_SYNC_FLUSH	(1 << 5)

#define ACTHD	        _MMIO(0x20c8)

#define ACTHD(base)	_MMIO((base) + 0xc8)

#define MEM_MODE	_MMIO(0x20cc)

#define MEM_MODE	_MMIO(0x20cc)

#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */

#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */

#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */

#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -3947,7 +3947,7 @@ enum i915_power_well_id { 
/*

/*

 * Logical Context regs

 * Logical Context regs

 */

 */

#define CCID				_MMIO(0x2180)

#define CCID(base)			_MMIO((base) + 0x180)

#define   CCID_EN			BIT(0)

#define   CCID_EN			BIT(0)

#define   CCID_EXTENDED_STATE_RESTORE	BIT(2)

#define   CCID_EXTENDED_STATE_RESTORE	BIT(2)

#define   CCID_EXTENDED_STATE_SAVE	BIT(3)

#define   CCID_EXTENDED_STATE_SAVE	BIT(3)

drivers/gpu/drm/i915/i915_reset.c

+9 −4
Original line number Original line Diff line number Diff line
@@ -1173,19 +1173,24 @@ static void i915_reset_device(struct drm_i915_private *i915, 
		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);

		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);

}

}





static void clear_register(struct drm_i915_private *dev_priv, i915_reg_t reg)

{

	I915_WRITE(reg, I915_READ(reg));

}



void i915_clear_error_registers(struct drm_i915_private *dev_priv)

void i915_clear_error_registers(struct drm_i915_private *dev_priv)

{

{

	u32 eir;

	u32 eir;





	if (!IS_GEN(dev_priv, 2))

	if (!IS_GEN(dev_priv, 2))

		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));

		clear_register(dev_priv, PGTBL_ER);





	if (INTEL_GEN(dev_priv) < 4)

	if (INTEL_GEN(dev_priv) < 4)

		I915_WRITE(IPEIR, I915_READ(IPEIR));

		clear_register(dev_priv, IPEIR(RENDER_RING_BASE));

	else

	else

		I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));

		clear_register(dev_priv, IPEIR_I965);





	I915_WRITE(EIR, I915_READ(EIR));

	clear_register(dev_priv, EIR);

	eir = I915_READ(EIR);

	eir = I915_READ(EIR);

	if (eir) {

	if (eir) {

		/*

		/*