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Commit 97a04e0d authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: switch intel_wait_for_register to uncore 



The intel_uncore structure is the owner of register access, so
subclass the function to it.

While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-9-daniele.ceraolospurio@intel.com
parent d2d551c0

drivers/gpu/drm/i915/i915_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -2687,7 +2687,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 
	if (!force_on)

		return 0;



	err = intel_wait_for_register(dev_priv,

	err = intel_wait_for_register(&dev_priv->uncore,

				      VLV_GTLC_SURVIVABILITY_REG,

				      VLV_GFX_CLK_STATUS_BIT,

				      VLV_GFX_CLK_STATUS_BIT,

drivers/gpu/drm/i915/i915_perf.c

+6 −6
Original line number Diff line number Diff line
@@ -1920,10 +1920,10 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream) 


static void gen7_oa_disable(struct i915_perf_stream *stream)

{

	struct drm_i915_private *dev_priv = stream->dev_priv;

	struct intel_uncore *uncore = &stream->dev_priv->uncore;



	I915_WRITE(GEN7_OACONTROL, 0);

	if (intel_wait_for_register(dev_priv,

	intel_uncore_write(uncore, GEN7_OACONTROL, 0);

	if (intel_wait_for_register(uncore,

				    GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,

				    50))

		DRM_ERROR("wait for OA to be disabled timed out\n");
@@ -1931,10 +1931,10 @@ static void gen7_oa_disable(struct i915_perf_stream *stream) 


static void gen8_oa_disable(struct i915_perf_stream *stream)

{

	struct drm_i915_private *dev_priv = stream->dev_priv;

	struct intel_uncore *uncore = &stream->dev_priv->uncore;



	I915_WRITE(GEN8_OACONTROL, 0);

	if (intel_wait_for_register(dev_priv,

	intel_uncore_write(uncore, GEN8_OACONTROL, 0);

	if (intel_wait_for_register(uncore,

				    GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,

				    50))

		DRM_ERROR("wait for OA to be disabled timed out\n");

drivers/gpu/drm/i915/icl_dsi.c

+4 −2
Original line number Diff line number Diff line
@@ -861,7 +861,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 
		I915_WRITE(PIPECONF(dsi_trans), tmp);



		/* wait for transcoder to be enabled */

		if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),

		if (intel_wait_for_register(&dev_priv->uncore,

					    PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE,

					    I965_PIPECONF_ACTIVE, 10))

			DRM_ERROR("DSI transcoder not enabled\n");
@@ -1039,7 +1040,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 
		I915_WRITE(PIPECONF(dsi_trans), tmp);



		/* wait for transcoder to be disabled */

		if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),

		if (intel_wait_for_register(&dev_priv->uncore,

					    PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE, 0, 50))

			DRM_ERROR("DSI trancoder not disabled\n");

	}

drivers/gpu/drm/i915/intel_cdclk.c

+6 −6
Original line number Diff line number Diff line
@@ -965,7 +965,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 


	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);



	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register(&dev_priv->uncore,

				    LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,

				    5))

		DRM_ERROR("DPLL0 not locked\n");
@@ -979,7 +979,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 
static void skl_dpll0_disable(struct drm_i915_private *dev_priv)

{

	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);

	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register(&dev_priv->uncore,

				    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,

				    1))

		DRM_ERROR("Couldn't disable DPLL0\n");
@@ -1324,7 +1324,7 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 
	I915_WRITE(BXT_DE_PLL_ENABLE, 0);



	/* Timeout 200us */

	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register(&dev_priv->uncore,

				    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,

				    1))

		DRM_ERROR("timeout waiting for DE PLL unlock\n");
@@ -1345,7 +1345,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 
	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);



	/* Timeout 200us */

	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register(&dev_priv->uncore,

				    BXT_DE_PLL_ENABLE,

				    BXT_DE_PLL_LOCK,

				    BXT_DE_PLL_LOCK,

drivers/gpu/drm/i915/intel_crt.c

+3 −3
Original line number Diff line number Diff line
@@ -435,7 +435,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 


		I915_WRITE(crt->adpa_reg, adpa);



		if (intel_wait_for_register(dev_priv,

		if (intel_wait_for_register(&dev_priv->uncore,

					    crt->adpa_reg,

					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,

					    1000))
@@ -489,7 +489,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 


	I915_WRITE(crt->adpa_reg, adpa);



	if (intel_wait_for_register(dev_priv,

	if (intel_wait_for_register(&dev_priv->uncore,

				    crt->adpa_reg,

				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,

				    1000)) {
@@ -542,7 +542,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) 
					      CRT_HOTPLUG_FORCE_DETECT,

					      CRT_HOTPLUG_FORCE_DETECT);

		/* wait for FORCE_DETECT to go off */

		if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,

		if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,

					    CRT_HOTPLUG_FORCE_DETECT, 0,

					    1000))

			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");