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Commit d2d551c0 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: intel_wait_for_register_fw to uncore 



The intel_uncore structure is the owner of register access, so
subclass the function to it.

While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-8-daniele.ceraolospurio@intel.com
parent 4319382e

drivers/gpu/drm/i915/i915_reset.c

+20 −16
Original line number Diff line number Diff line
@@ -245,10 +245,12 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv, 
			     unsigned int engine_mask,

			     unsigned int retry)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	int ret;



	I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);

	ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,

	intel_uncore_write_fw(uncore, ILK_GDSR,

			      ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);

	ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,

					   ILK_GRDOM_RESET_ENABLE, 0,

					   5000, 0,

					   NULL);
@@ -257,8 +259,9 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv, 
		goto out;

	}



	I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);

	ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,

	intel_uncore_write_fw(uncore, ILK_GDSR,

			      ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);

	ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,

					   ILK_GRDOM_RESET_ENABLE, 0,

					   5000, 0,

					   NULL);
@@ -268,8 +271,8 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv, 
	}



out:

	I915_WRITE_FW(ILK_GDSR, 0);

	POSTING_READ_FW(ILK_GDSR);

	intel_uncore_write_fw(uncore, ILK_GDSR, 0);

	intel_uncore_posting_read_fw(uncore, ILK_GDSR);

	return ret;

}
@@ -277,6 +280,7 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv, 
static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,

				u32 hw_domain_mask)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	int err;



	/*
@@ -284,10 +288,10 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, 
	 * for fifo space for the write or forcewake the chip for

	 * the read

	 */

	I915_WRITE_FW(GEN6_GDRST, hw_domain_mask);

	intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);



	/* Wait for the device to ack the reset requests */

	err = __intel_wait_for_register_fw(dev_priv,

	err = __intel_wait_for_register_fw(uncore,

					   GEN6_GDRST, hw_domain_mask, 0,

					   500, 0,

					   NULL);
@@ -330,6 +334,7 @@ static int gen6_reset_engines(struct drm_i915_private *i915, 
static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,

			  struct intel_engine_cs *engine)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;

	i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;

	u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
@@ -377,10 +382,9 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, 
	 * ends up being locked to the engine we want to reset, we have to reset

	 * it as well (we will unlock it once the reset sequence is completed).

	 */

	I915_WRITE_FW(sfc_forced_lock,

		      I915_READ_FW(sfc_forced_lock) | sfc_forced_lock_bit);

	intel_uncore_rmw_or_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);



	if (__intel_wait_for_register_fw(dev_priv,

	if (__intel_wait_for_register_fw(uncore,

					 sfc_forced_lock_ack,

					 sfc_forced_lock_ack_bit,

					 sfc_forced_lock_ack_bit,
@@ -389,7 +393,7 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, 
		return 0;

	}



	if (I915_READ_FW(sfc_usage) & sfc_usage_bit)

	if (intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit)

		return sfc_reset_bit;



	return 0;
@@ -465,13 +469,13 @@ static int gen11_reset_engines(struct drm_i915_private *i915, 


static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct intel_uncore *uncore = &engine->i915->uncore;

	int ret;



	I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),

	intel_uncore_write_fw(uncore, RING_RESET_CTL(engine->mmio_base),

			      _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));



	ret = __intel_wait_for_register_fw(dev_priv,

	ret = __intel_wait_for_register_fw(uncore,

					   RING_RESET_CTL(engine->mmio_base),

					   RESET_CTL_READY_TO_RESET,

					   RESET_CTL_READY_TO_RESET,

drivers/gpu/drm/i915/intel_dpio_phy.c

+2 −1
Original line number Diff line number Diff line
@@ -383,7 +383,8 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
	 * The flag should get set in 100us according to the HW team, but

	 * use 1ms due to occasional timeouts observed with that.

	 */

	if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),

	if (intel_wait_for_register_fw(&dev_priv->uncore,

				       BXT_PORT_CL1CM_DW0(phy),

				       PHY_RESERVED | PHY_POWER_GOOD,

				       PHY_POWER_GOOD,

				       1))

drivers/gpu/drm/i915/intel_engine_cs.c

+5 −5
Original line number Diff line number Diff line
@@ -817,20 +817,20 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) 


int intel_engine_stop_cs(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct intel_uncore *uncore = &engine->i915->uncore;

	const u32 base = engine->mmio_base;

	const i915_reg_t mode = RING_MI_MODE(base);

	int err;



	if (INTEL_GEN(dev_priv) < 3)

	if (INTEL_GEN(engine->i915) < 3)

		return -ENODEV;



	GEM_TRACE("%s\n", engine->name);



	I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));

	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));



	err = 0;

	if (__intel_wait_for_register_fw(dev_priv,

	if (__intel_wait_for_register_fw(uncore,

					 mode, MODE_IDLE, MODE_IDLE,

					 1000, 0,

					 NULL)) {
@@ -839,7 +839,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) 
	}



	/* A final mmio read to let GPU writes be hopefully flushed to memory */

	POSTING_READ_FW(mode);

	intel_uncore_posting_read_fw(uncore, mode);



	return err;

}

drivers/gpu/drm/i915/intel_guc.c

+6 −5
Original line number Diff line number Diff line
@@ -398,6 +398,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 
			u32 *response_buf, u32 response_buf_size)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 status;

	int i;

	int ret;
@@ -414,12 +415,12 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 
		*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);



	mutex_lock(&guc->send_mutex);

	intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);

	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);



	for (i = 0; i < len; i++)

		I915_WRITE(guc_send_reg(guc, i), action[i]);

		intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);



	POSTING_READ(guc_send_reg(guc, i - 1));

	intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));



	intel_guc_notify(guc);
@@ -427,7 +428,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 
	 * No GuC command should ever take longer than 10ms.

	 * Fast commands should still complete in 10us.

	 */

	ret = __intel_wait_for_register_fw(dev_priv,

	ret = __intel_wait_for_register_fw(uncore,

					   guc_send_reg(guc, 0),

					   INTEL_GUC_MSG_TYPE_MASK,

					   INTEL_GUC_MSG_TYPE_RESPONSE <<
@@ -454,7 +455,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 
	ret = INTEL_GUC_MSG_TO_DATA(status);



out:

	intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);

	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);

	mutex_unlock(&guc->send_mutex);



	return ret;

drivers/gpu/drm/i915/intel_huc_fw.c

+16 −11
Original line number Diff line number Diff line
@@ -106,41 +106,46 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) 
{

	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);

	struct drm_i915_private *dev_priv = huc_to_i915(huc);

	struct intel_uncore *uncore = &dev_priv->uncore;

	unsigned long offset = 0;

	u32 size;

	int ret;



	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);



	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);

	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);



	/* Set the source address for the uCode */

	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +

		 huc_fw->header_offset;

	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));

	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);

	intel_uncore_write(uncore, DMA_ADDR_0_LOW,

			   lower_32_bits(offset));

	intel_uncore_write(uncore, DMA_ADDR_0_HIGH,

			   upper_32_bits(offset) & 0xFFFF);



	/* Hardware doesn't look at destination address for HuC. Set it to 0,

	/*

	 * Hardware doesn't look at destination address for HuC. Set it to 0,

	 * but still program the correct address space.

	 */

	I915_WRITE(DMA_ADDR_1_LOW, 0);

	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);

	intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);

	intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);



	size = huc_fw->header_size + huc_fw->ucode_size;

	I915_WRITE(DMA_COPY_SIZE, size);

	intel_uncore_write(uncore, DMA_COPY_SIZE, size);



	/* Start the DMA */

	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));

	intel_uncore_write(uncore, DMA_CTRL,

			   _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));



	/* Wait for DMA to finish */

	ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);

	ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);



	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);



	/* Disable the bits once DMA is over */

	I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));

	intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));



	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);

	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);



	return ret;

}