Merge remote-tracking branch 'scott/next' into next

cores and peripheral IP blocks.

Please refer to the Reference Manual for details.

All references to "1.0" and "2.0" refer to the QorIQ chassis version to

which the chip complies.

Chassis Version		Example Chips

---------------		-------------

1.0			p4080, p5020, p5040

2.0			t4240, b4860, t1040

1. Clock Block Binding

Required properties:

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		}

		};

		pll0: pll0@800 {

			#clock-cells = <1>;

KEYMILE bfticu Chassis Management FPGA

The bfticu is a multifunction device that manages the whole chassis.

Its main functionality is to collect IRQs from the whole chassis and signals

them to a single controller.

Required properties:

- compatible: "keymile,bfticu"

- interrupt-controller: the bfticu FPGA is an interrupt controller

- interrupts: the main IRQ line to signal the collected IRQs

- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant

  of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to

- reg: access on the parent local bus (chip select, offset in chip select, size)

Example:

	chassis-mgmt@3,0 {

		compatible = "keymile,bfticu";

		interrupt-controller;

		#interrupt-cells = <2>;

		reg = <3 0 0x100>;

		interrupt-parent = <&mpic>;

		interrupts = <6 1 0 0>;

	};

KEYMILE qrio Board Control CPLD

The qrio is a multifunction device that controls the KEYMILE boards based on

the kmp204x design.

It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable

GPIO blocks.

Required properties:

- compatible: "keymile,qriox"

- reg: access on the parent local bus (chip select, offset in chip select, size)

Example:

	board-control@1,0 {

		compatible = "keymile,qriox";

		reg = <1 0 0x80>;

	};

			gpio-controller;

		};

	};

* Freescale on-board FPGA connected on I2C bus

Some Freescale boards like BSC9132QDS have on board FPGA connected on

the i2c bus.

Required properties:

- compatible: Should be a board-specific string followed by a string

  indicating the type of FPGA.  Example:

	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"

- reg: Should contain the address of the FPGA

Example:

	fpga: fpga@66 {

		compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";

		reg = <0x66>;

	};

Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding

DESCRIPTION

The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure

that enables the implementation of coherent, multicore systems.

Required properties:

- compatible: <string list>

		fsl,corenet1-cf - CoreNet coherency fabric version 1.

		Example chips: T4240, B4860

		fsl,corenet2-cf - CoreNet coherency fabric version 2.

		Example chips: P5040, P5020, P4080, P3041, P2041

		fsl,corenet-cf - Used to represent the common registers

		between CCF version 1 and CCF version 2.  This compatible

		is retained for compatibility reasons, as it was already

		used for both CCF version 1 chips and CCF version 2

		chips.  It should be specified after either

		"fsl,corenet1-cf" or "fsl,corenet2-cf".

- reg: <prop-encoded-array>

		A standard property. Represents the CCF registers.

- interrupts: <prop-encoded-array>

		Interrupt mapping for CCF error interrupt.

- fsl,ccf-num-csdids: <u32>

		Specifies the number of Coherency Subdomain ID Port Mapping

		Registers that are supported by the CCF.

- fsl,ccf-num-snoopids: <u32>

		Specifies the number of Snoop ID Port Mapping Registers that

		are supported by CCF.

Example:

	corenet-cf@18000 {

		compatible = "fsl,corenet2-cf", "fsl,corenet-cf";

		reg = <0x18000 0x1000>;

		interrupts = <16 2 1 31>;

		fsl,ccf-num-csdids = <32>;

		fsl,ccf-num-snoopids = <32>;

	};