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Commit e83eb028 authored by Scott Wood's avatar Scott Wood
Browse files

powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips 



Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Cc: Diana Craciun <diana.craciun@freescale.com>
parent 8cb59788

arch/powerpc/boot/dts/fsl/p2041si-post.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -262,6 +262,7 @@ 
		interrupts = <

			24 2 0 0

			16 2 1 30>;

		fsl,portid-mapping = <0x0f000000>;



		pamu0: pamu@0 {

			reg = <0 0x1000>;

arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ 
			reg = <0>;

			clocks = <&mux0>;

			next-level-cache = <&L2_0>;

			fsl,portid-mapping = <0x80000000>;

			L2_0: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -92,6 +93,7 @@ 
			reg = <1>;

			clocks = <&mux1>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x40000000>;

			L2_1: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -101,6 +103,7 @@ 
			reg = <2>;

			clocks = <&mux2>;

			next-level-cache = <&L2_2>;

			fsl,portid-mapping = <0x20000000>;

			L2_2: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -110,6 +113,7 @@ 
			reg = <3>;

			clocks = <&mux3>;

			next-level-cache = <&L2_3>;

			fsl,portid-mapping = <0x10000000>;

			L2_3: l2-cache {

				next-level-cache = <&cpc>;

			};

arch/powerpc/boot/dts/fsl/p3041si-post.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -289,6 +289,7 @@ 
		interrupts = <

			24 2 0 0

			16 2 1 30>;

		fsl,portid-mapping = <0x0f000000>;



		pamu0: pamu@0 {

			reg = <0 0x1000>;

arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ 
			reg = <0>;

			clocks = <&mux0>;

			next-level-cache = <&L2_0>;

			fsl,portid-mapping = <0x80000000>;

			L2_0: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -93,6 +94,7 @@ 
			reg = <1>;

			clocks = <&mux1>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x40000000>;

			L2_1: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -102,6 +104,7 @@ 
			reg = <2>;

			clocks = <&mux2>;

			next-level-cache = <&L2_2>;

			fsl,portid-mapping = <0x20000000>;

			L2_2: l2-cache {

				next-level-cache = <&cpc>;

			};
@@ -111,6 +114,7 @@ 
			reg = <3>;

			clocks = <&mux3>;

			next-level-cache = <&L2_3>;

			fsl,portid-mapping = <0x10000000>;

			L2_3: l2-cache {

				next-level-cache = <&cpc>;

			};

arch/powerpc/boot/dts/fsl/p4080si-post.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ 
		interrupts = <

			24 2 0 0

			16 2 1 30>;

		fsl,portid-mapping = <0x00f80000>;



		pamu0: pamu@0 {

			reg = <0 0x1000>;