thermal: qcom-spmi-temp-alarm: align temp readings with over-temp stage

Ensure that the PMIC temperature reported is at least the lowest
value possible for the current over-temperature stage.

This guarantees that we cannot hit the following corner case on
PMICs that have a GEN2 TEMP_ALARM peripheral:

0. The PMIC's thermal zone device tree configuration defines a
   passive trip point equal to the stage 1 over-temperature
   threshold (e.g. 95 C) and hysteresis=0, along with
   polling-delay=0 and polling-delay-passive>0.

1. The PMIC heats up and reaches 95 C at which point the over-
   temperature stage transitions from 0 to 1.

2. The PMIC triggers the TEMP_ALARM IRQ (which only occurs for
   over-temperature stage 0 -> 1 and 1 -> 0 transitions on GEN2
   peripherals).

3. The qcom-spmi-temp-alarm IRQ handler signals to the thermal
   framework that an event has occurred.

4. The thermal framework reads the PMIC temperature (via ADC).

5. If the temperature reported by the ADC is less than 95 C
   (e.g. 94.99 C), then no further action is taken.

6. The PMIC temperature can continue to increase without software
   awareness.

7. Eventually the PMIC temperature can hit the stage 3 over-
   temperature level (e.g. 145 C) at which point the PMIC abruptly
   shuts down the system.

This situation is avoided if at step #5, the qcom-spmi-temp-alarm
driver instead reports a temperature of 95 C (which is the minimum
possible for over-temperature stage 1) instead of the slightly low
ADC temperature reading.  Doing so causes the thermal framework to
switch to passive polling of the PMIC temperature.  This ensures
that further increase of the PMIC temperature is directly observed
by software.  That way, an orderly shutdown can be initiated by
software if needed before hitting over-temperature stage 3.

Change-Id: Ia4d12f092fb06970d686b830051788430afd32dc
Signed-off-by: David Collins <collinsd@codeaurora.org>