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Commit b335d89c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-devel-hwmod-data-for-v3.5' of... 

Merge tag 'omap-devel-hwmod-data-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm

Data changes related to omap hwmod

By Paul Walmsley (4) and others
via Paul Walmsley (1) and Tony Lindgren (1)
* tag 'omap-devel-hwmod-data-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset
  ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database
  ARM: OMAP4: hwmod_data: Name the common irq for McBSP ports
  ARM: OMAP4: hwmod data: I2C: add flag for context restore
  ARM: OMAP3: hwmod_data: Rename the common irq for McBSP ports
  ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmod
  ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod
  ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data
  ARM: OMAP2+: HDQ1W: add custom reset function
  ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420
parents 620340ca bfd17879

arch/arm/mach-omap2/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 


# Common support

obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \

	 common.o gpio.o dma.o wd_timer.o display.o i2c.o

	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o



omap-2-3-common				= irq.o sdrc.o

hwmod-common				= omap_hwmod.o \
@@ -189,6 +189,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),) 
obj-y					+= dsp.o

endif



# OMAP2420 MSDI controller integration support ("MMC")

obj-$(CONFIG_SOC_OMAP2420)		+= msdi.o



# Specific board support

obj-$(CONFIG_MACH_OMAP_GENERIC)		+= board-generic.o

obj-$(CONFIG_MACH_OMAP_H4)		+= board-h4.o

arch/arm/mach-omap2/hdq1w.c

0 → 100644
+72 −0
Original line number Diff line number Diff line 
/*

 * IP block integration code for the HDQ1W/1-wire IP block

 *

 * Copyright (C) 2012 Texas Instruments, Inc.

 * Paul Walmsley

 *

 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by

 *     Avinash.H.M <avinashhm@ti.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA

 * 02110-1301 USA

 */



#include <plat/omap_hwmod.h>

#include <plat/hdq1w.h>



#include "common.h"



/* Maximum microseconds to wait for OMAP module to softreset */

#define MAX_MODULE_SOFTRESET_WAIT	10000



/**

 * omap_hdq1w_reset - reset the OMAP HDQ1W module

 * @oh: struct omap_hwmod *

 *

 * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire

 * Software Reset" of the OMAP34xx Technical Reference Manual Revision

 * ZR (SWPU223R) does not include the rather important fact that, for

 * the reset to succeed, the HDQ1W module's internal clock gate must be

 * programmed to allow the clock to propagate to the rest of the

 * module.  In this sense, it's rather similar to the I2C custom reset

 * function.  Returns 0.

 */

int omap_hdq1w_reset(struct omap_hwmod *oh)

{

	u32 v;

	int c = 0;



	/* Write to the SOFTRESET bit */

	omap_hwmod_softreset(oh);



	/* Enable the module's internal clocks */

	v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);

	v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;

	omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);



	/* Poll on RESETDONE bit */

	omap_test_timeout((omap_hwmod_read(oh,

					   oh->class->sysc->syss_offs)

			   & SYSS_RESETDONE_MASK),

			  MAX_MODULE_SOFTRESET_WAIT, c);



	if (c == MAX_MODULE_SOFTRESET_WAIT)

		pr_warning("%s: %s: softreset failed (waited %d usec)\n",

			   __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);

	else

		pr_debug("%s: %s: softreset in %d usec\n", __func__,

			 oh->name, c);



	return 0;

}

arch/arm/mach-omap2/io.c

+0 −18
Original line number Diff line number Diff line
@@ -363,24 +363,6 @@ static void __init omap_hwmod_init_postsetup(void) 
#endif

	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);



	/*

	 * Set the default postsetup state for unusual modules (like

	 * MPU WDT).

	 *

	 * The postsetup_state is not actually used until

	 * omap_hwmod_late_init(), so boards that desire full watchdog

	 * coverage of kernel initialization can reprogram the

	 * postsetup_state between the calls to

	 * omap2_init_common_infra() and omap_sdrc_init().

	 *

	 * XXX ideally we could detect whether the MPU WDT was currently

	 * enabled here and make this conditional

	 */

	postsetup_state = _HWMOD_STATE_DISABLED;

	omap_hwmod_for_each_by_class("wd_timer",

				     _set_hwmod_postsetup_state,

				     &postsetup_state);



	omap_pm_if_early_init();

}

arch/arm/mach-omap2/msdi.c

0 → 100644
+88 −0
Original line number Diff line number Diff line 
/*

 * MSDI IP block reset

 *

 * Copyright (C) 2012 Texas Instruments, Inc.

 * Paul Walmsley

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA

 * 02110-1301 USA

 *

 * XXX What about pad muxing?

 */



#include <linux/kernel.h>



#include <plat/omap_hwmod.h>

#include <plat/mmc.h>



#include "common.h"



/*

 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register

 *     from the IP block's base address

 */

#define MSDI_CON_OFFSET				0x0c



/* Register bitfields in the CON register */

#define MSDI_CON_POW_MASK			BIT(11)

#define MSDI_CON_CLKD_MASK			(0x3f << 0)

#define MSDI_CON_CLKD_SHIFT			0



/* Maximum microseconds to wait for OMAP module to softreset */

#define MAX_MODULE_SOFTRESET_WAIT	10000



/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */

#define MSDI_TARGET_RESET_CLKD		0x3ff



/**

 * omap_msdi_reset - reset the MSDI IP block

 * @oh: struct omap_hwmod *

 *

 * The MSDI IP block on OMAP2420 has to have both the POW and CLKD

 * fields set inside its CON register for a reset to complete

 * successfully.  This is not documented in the TRM.  For CLKD, we use

 * the value that results in the lowest possible clock rate, to attempt

 * to avoid disturbing any cards.

 */

int omap_msdi_reset(struct omap_hwmod *oh)

{

	u16 v = 0;

	int c = 0;



	/* Write to the SOFTRESET bit */

	omap_hwmod_softreset(oh);



	/* Enable the MSDI core and internal clock */

	v |= MSDI_CON_POW_MASK;

	v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;

	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);



	/* Poll on RESETDONE bit */

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)

			   & SYSS_RESETDONE_MASK),

			  MAX_MODULE_SOFTRESET_WAIT, c);



	if (c == MAX_MODULE_SOFTRESET_WAIT)

		pr_warning("%s: %s: softreset failed (waited %d usec)\n",

			   __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);

	else

		pr_debug("%s: %s: softreset in %d usec\n", __func__,

			 oh->name, c);



	/* Disable the MSDI internal clock */

	v &= ~MSDI_CON_CLKD_MASK;

	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);



	return 0;

}

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+112 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <plat/dmtimer.h>

#include <plat/l3_2xxx.h>

#include <plat/l4_2xxx.h>

#include <plat/mmc.h>



#include "omap_hwmod_common_data.h"
@@ -239,6 +240,67 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { 
	},

};



static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {

	.rev_offs	= 0x3c,

	.sysc_offs	= 0x64,

	.syss_offs	= 0x68,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_msdi_hwmod_class = {

	.name	= "msdi",

	.sysc	= &omap2420_msdi_sysc,

	.reset	= &omap_msdi_reset,

};



/* msdi1 */

static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {

	{ .irq = 83 },

	{ .irq = -1 }

};



static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */

	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */

	{ .dma_req = -1 }

};



static struct omap_hwmod omap2420_msdi1_hwmod = {

	.name		= "msdi1",

	.class		= &omap2420_msdi_hwmod_class,

	.mpu_irqs	= omap2420_msdi1_irqs,

	.sdma_reqs	= omap2420_msdi1_sdma_reqs,

	.main_clk	= "mmc_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_MMC_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,

		},

	},

	.flags		= HWMOD_16BIT_REG,

};



/* HDQ1W/1-wire */

static struct omap_hwmod omap2420_hdq1w_hwmod = {

	.name		= "hdq1w",

	.mpu_irqs	= omap2_hdq1w_mpu_irqs,

	.main_clk	= "hdq_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_HDQ_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,

		},

	},

	.class		= &omap2_hdq1w_class,

};



/*

 * interfaces

 */
@@ -428,6 +490,53 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {

	{

		.pa_start	= 0x4809c000,

		.pa_end		= 0x4809c000 + SZ_128 - 1,

		.flags		= ADDR_TYPE_RT,

	},

	{ }

};



/* l4_core -> msdi1 */

static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2420_msdi1_hwmod,

	.clk		= "mmc_ick",

	.addr		= omap2420_msdi1_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> hdq1w interface */

static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2420_hdq1w_hwmod,

	.clk		= "hdq_ick",

	.addr		= omap2_hdq1w_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,

};





/* l4_wkup -> 32ksync_counter */

static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {

	{

		.pa_start	= 0x48004000,

		.pa_end		= 0x4800401f,

		.flags		= ADDR_TYPE_RT

	},

	{ }

};



static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {

	.master		= &omap2xxx_l4_wkup_hwmod,

	.slave		= &omap2xxx_counter_32k_hwmod,

	.clk		= "sync_32k_ick",

	.addr		= omap2420_counter_32k_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {

	&omap2xxx_l3_main__l4_core,

	&omap2xxx_mpu__l3_main,
@@ -468,6 +577,9 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { 
	&omap2420_l4_core__mailbox,

	&omap2420_l4_core__mcbsp1,

	&omap2420_l4_core__mcbsp2,

	&omap2420_l4_core__msdi1,

	&omap2420_l4_core__hdq1w,

	&omap2420_l4_wkup__counter_32k,

	NULL,

};