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Commit b28d7356 authored May 15, 2020 by qctecmdr Committed by Gerrit - the friendly Code Review server May 15, 2020

Merge "ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL on lahaina"

parents ca13e22c 4ce97d38

qcom/lahaina-pcie.dtsi

+35 −7

Original line number	Diff line number	Diff line
		@@ -109,7 +109,12 @@
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;

		qcom,pcie-phy-ver = <10921>;
		qcom,phy-manage-pll = <1>;
		qcom,phy-resetsm-cntrl2 = <0xa0>;
		qcom,phy-core-pll-en-mux = <7>;
		qcom,phy-c-ready-status = <0x178>;

		qcom,pcie-phy-ver = <10971>;
		qcom,phy-status-offset = <0x214>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x240>;
		@@ -144,26 +149,49 @@
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