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Commit 4ce97d38 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL on lahaina 

PCIe0 needs to manage PHY PLL on lahaina. Therefore add the DT
entries so that PCIe0 has to correct information to support this
request.

Change-Id: I622b4d3dc24e530554c23cbeeb0ee6dd528e5587
parent 4dfb4bb8

qcom/lahaina-pcie.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -109,6 +109,11 @@ 
		qcom,slv-addr-space-size = <0x4000000>;

		qcom,ep-latency = <10>;



		qcom,phy-manage-pll = <1>;

		qcom,phy-resetsm-cntrl2 = <0xa0>;

		qcom,phy-core-pll-en-mux = <7>;

		qcom,phy-c-ready-status = <0x178>;



		qcom,pcie-phy-ver = <10971>;

		qcom,phy-status-offset = <0x214>;

		qcom,phy-status-bit = <6>;