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Commit b2342e4e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: clk-alpha-pll: Add support for Huayra print registers"

parents 521e5186 3cfeff42

drivers/clk/qcom/clk-alpha-pll.c

+183 −0
Original line number Diff line number Diff line
@@ -1377,6 +1377,61 @@ static void clk_alpha_pll_init(struct clk_hw *hw) 
		rclk->ops = &clk_alpha_pll_regmap_ops;

}



static void clk_alpha_pll_huayra_list_registers(struct seq_file *f,

							struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},

		{"PLL_OPMODE", PLL_OFF_OPMODE},

		{"PLL_STATUS", PLL_OFF_STATUS},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],

								&val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

				data1[0].offset, &val);

		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);

	}

}



static struct clk_regmap_ops clk_alpha_pll_huayra_regmap_ops = {

	.list_registers = clk_alpha_pll_huayra_list_registers,

};



static void clk_alpha_pll_huayra_init(struct clk_hw *hw)

{

	struct clk_regmap *rclk = to_clk_regmap(hw);



	if (!rclk->ops)

		rclk->ops = &clk_alpha_pll_huayra_regmap_ops;

}



const struct clk_ops clk_alpha_pll_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,
@@ -1407,6 +1462,8 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { 
	.recalc_rate = alpha_pll_huayra_recalc_rate,

	.round_rate = alpha_pll_huayra_round_rate,

	.set_rate = alpha_pll_huayra_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_alpha_pll_huayra_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -1447,6 +1504,61 @@ const struct clk_ops clk_trion_fixed_pll_ops = { 
};

EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);



static void clk_alpha_pll_zonda_list_registers(struct seq_file *f,

							struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},

		{"PLL_OPMODE", PLL_OFF_OPMODE},

		{"PLL_STATUS", PLL_OFF_STATUS},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],

								&val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

				data1[0].offset, &val);

		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);

	}

}



static struct clk_regmap_ops clk_alpha_pll_zonda_regmap_ops = {

	.list_registers = clk_alpha_pll_zonda_list_registers,

};



static void clk_alpha_pll_zonda_init(struct clk_hw *hw)

{

	struct clk_regmap *rclk = to_clk_regmap(hw);



	if (!rclk->ops)

		rclk->ops = &clk_alpha_pll_zonda_regmap_ops;

}



const struct clk_ops clk_alpha_pll_zonda_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,
@@ -1458,6 +1570,8 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { 
	.recalc_rate = clk_zonda_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_zonda_pll_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_alpha_pll_zonda_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -1475,6 +1589,11 @@ const struct clk_ops clk_alpha_pll_zonda_5lpe_ops = { 
	.recalc_rate = clk_zonda_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_zonda_pll_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_alpha_pll_zonda_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

};

EXPORT_SYMBOL(clk_alpha_pll_zonda_5lpe_ops);
@@ -2525,6 +2644,64 @@ static int alpha_pll_lucid_is_enabled(struct clk_hw *hw) 
	return lucid_pll_is_enabled(pll, pll->clkr.regmap);

}



static void lucid_pll_list_registers(struct seq_file *f,

		struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},

		{"PLL_USER_CTL_U1", PLL_OFF_USER_CTL_U1},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},

		{"PLL_STATUS", PLL_OFF_STATUS},

		{"PLL_OPMODE", PLL_OFF_OPMODE},

		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[0].offset], &val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

					data1[0].offset, &val);

		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);

	}

}



static struct clk_regmap_ops clk_lucid_pll_regmap_ops = {

	.list_registers = &lucid_pll_list_registers,

};



static void clk_lucid_pll_init(struct clk_hw *hw)

{

	struct clk_regmap *rclk = to_clk_regmap(hw);



	if (!rclk->ops)

		rclk->ops = &clk_lucid_pll_regmap_ops;

}



const struct clk_ops clk_alpha_pll_lucid_ops = {

	.prepare = alpha_pll_lucid_prepare,

	.unprepare = clk_unprepare_regmap,
@@ -2536,6 +2713,8 @@ const struct clk_ops clk_alpha_pll_lucid_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2554,6 +2733,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 
	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_5lpe_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2570,6 +2750,8 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { 
	.is_enabled = alpha_pll_lucid_is_enabled,

	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif
@@ -2594,6 +2776,7 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_lucid_pll_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

drivers/clk/qcom/clk-alpha-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ enum { 
};



enum {

	PLL_OFF_MODE,

	PLL_OFF_L_VAL,

	PLL_OFF_CAL_L_VAL,

	PLL_OFF_ALPHA_VAL,