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Commit 3cfeff42 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: clk-alpha-pll: Add support for Huayra print registers 



Huayra PLL print registers are required to get the PLL values from
the debugfs, thus add support for the same.

Change-Id: I439f64646d5995943cf8d0ef94daf3f85cd0ae45
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent f299e23e

drivers/clk/qcom/clk-alpha-pll.c

+57 −0
Original line number Diff line number Diff line
@@ -1377,6 +1377,61 @@ static void clk_alpha_pll_init(struct clk_hw *hw) 
		rclk->ops = &clk_alpha_pll_regmap_ops;

}



static void clk_alpha_pll_huayra_list_registers(struct seq_file *f,

							struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_ALPHA_VAL", PLL_OFF_ALPHA_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_CONFIG_CTL_U1", PLL_OFF_CONFIG_CTL_U1},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_TEST_CTL_U1", PLL_OFF_TEST_CTL_U1},

		{"PLL_OPMODE", PLL_OFF_OPMODE},

		{"PLL_STATUS", PLL_OFF_STATUS},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],

								&val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

				data1[0].offset, &val);

		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);

	}

}



static struct clk_regmap_ops clk_alpha_pll_huayra_regmap_ops = {

	.list_registers = clk_alpha_pll_huayra_list_registers,

};



static void clk_alpha_pll_huayra_init(struct clk_hw *hw)

{

	struct clk_regmap *rclk = to_clk_regmap(hw);



	if (!rclk->ops)

		rclk->ops = &clk_alpha_pll_huayra_regmap_ops;

}



const struct clk_ops clk_alpha_pll_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,
@@ -1407,6 +1462,8 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { 
	.recalc_rate = alpha_pll_huayra_recalc_rate,

	.round_rate = alpha_pll_huayra_round_rate,

	.set_rate = alpha_pll_huayra_set_rate,

	.debug_init = clk_common_debug_init,

	.init = clk_alpha_pll_huayra_init,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif