ARM: dts: msm: Enable SMMU bypass mode for stage 1 of UFS

Enable SMMU in bypass mode for stage1 of UFS.

Change-Id: I0515f1d69ec225c382d12a5e05e10a326e16382c

parent 05f34477

qcom/shima.dtsi

+5 −0

Original line number	Diff line number	Diff line
		@@ -1167,6 +1167,11 @@
		reset-gpios = <&tlmm 204 GPIO_ACTIVE_LOW>;
		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		iommus = <&apps_smmu 0x80 0x0>;
		qcom,iommu-dma = "bypass";
		dma-coherent;

		status = "disabled";
		};