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Commit 05f34477 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update Graphics clock controller node for HOLI"

parents 329c91a8 484a609b

qcom/holi-gdsc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@599106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x599106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -109,7 +109,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@599100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x599100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

qcom/holi.dtsi

+13 −5
Original line number Diff line number Diff line
@@ -633,8 +633,18 @@ 
	};



	gpucc: qcom,gpucc@5990000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		compatible = "qcom,holi-gpucc";

		reg = <0x5990000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_gx-supply = <&VDD_GFX_LEVEL>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,

			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,

			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

		clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",

				"gcc_gpu_gpll0_div_clk_src",

				"gcc_gpu_snoc_dvm_gfx_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1458,12 +1468,10 @@ 


&gpu_cx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	vdd_parent-supply = <&VDD_CX_LEVEL>;

	status = "ok";

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_CX_LEVEL>;

	vdd_parent-supply = <&VDD_CX_LEVEL>;

	parent-supply = <&VDD_GFX_LEVEL>;

	status = "ok";

};