Loading drivers/clk/qcom/clk-alpha-pll.c +6 −6 Original line number Diff line number Diff line Loading @@ -791,7 +791,7 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, */ if (is_enabled(&pll->clkr.hw) && !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) hw->init->ops->disable(hw); clk_alpha_pll_disable(hw); regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); Loading Loading @@ -830,9 +830,9 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, (pll->flags & SUPPORTS_DYNAMIC_UPDATE)) clk_alpha_pll_dynamic_update(pll); if (is_enabled(&pll->clkr.hw) && if (!is_enabled(&pll->clkr.hw) && !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) hw->init->ops->enable(hw); clk_alpha_pll_enable(hw); return clk_alpha_pll_update_latch(pll, is_enabled); } Loading Loading @@ -1763,8 +1763,8 @@ static void clk_alpha_pll_list_registers(struct seq_file *f, struct clk_hw *hw) size = ARRAY_SIZE(data); for (i = 0; i < size; i++) { regmap_read(pll->clkr.regmap, pll->offset + data[i].offset, &val); regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[i].offset], &val); clock_debug_output(f, "%20s: 0x%.8x\n", data[i].name, val); } Loading Loading @@ -4411,7 +4411,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", hw->init->name, clk_hw_get_rate(hw), freq_hz); clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); /* Setup the PLL for the new frequency */ a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); Loading drivers/clk/qcom/clk-regmap.c +13 −0 Original line number Diff line number Diff line Loading @@ -286,6 +286,19 @@ int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) } EXPORT_SYMBOL_GPL(devm_clk_register_regmap); /** * devm_clk_regmap_list_node - Add a clk-regmap clock list for providers * * @rclk: clk to operate on * * Maintain clk-regmap clks list for providers use. */ void devm_clk_regmap_list_node(struct device *dev, struct clk_regmap *rclk) { list_add(&rclk->list_node, &clk_regmap_list); } EXPORT_SYMBOL(devm_clk_regmap_list_node); int clk_runtime_get_regmap(struct clk_regmap *rclk) { int ret; Loading drivers/clk/qcom/clk-regmap.h +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ int clk_pre_change_regmap(struct clk_hw *hw, unsigned long cur_rate, int clk_post_change_regmap(struct clk_hw *hw, unsigned long old_rate, unsigned long cur_rate); int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); void devm_clk_regmap_list_node(struct device *dev, struct clk_regmap *rclk); bool clk_is_regmap_clk(struct clk_hw *hw); Loading Loading
drivers/clk/qcom/clk-alpha-pll.c +6 −6 Original line number Diff line number Diff line Loading @@ -791,7 +791,7 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, */ if (is_enabled(&pll->clkr.hw) && !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) hw->init->ops->disable(hw); clk_alpha_pll_disable(hw); regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); Loading Loading @@ -830,9 +830,9 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, (pll->flags & SUPPORTS_DYNAMIC_UPDATE)) clk_alpha_pll_dynamic_update(pll); if (is_enabled(&pll->clkr.hw) && if (!is_enabled(&pll->clkr.hw) && !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) hw->init->ops->enable(hw); clk_alpha_pll_enable(hw); return clk_alpha_pll_update_latch(pll, is_enabled); } Loading Loading @@ -1763,8 +1763,8 @@ static void clk_alpha_pll_list_registers(struct seq_file *f, struct clk_hw *hw) size = ARRAY_SIZE(data); for (i = 0; i < size; i++) { regmap_read(pll->clkr.regmap, pll->offset + data[i].offset, &val); regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[i].offset], &val); clock_debug_output(f, "%20s: 0x%.8x\n", data[i].name, val); } Loading Loading @@ -4411,7 +4411,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", hw->init->name, clk_hw_get_rate(hw), freq_hz); clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); /* Setup the PLL for the new frequency */ a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); Loading
drivers/clk/qcom/clk-regmap.c +13 −0 Original line number Diff line number Diff line Loading @@ -286,6 +286,19 @@ int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) } EXPORT_SYMBOL_GPL(devm_clk_register_regmap); /** * devm_clk_regmap_list_node - Add a clk-regmap clock list for providers * * @rclk: clk to operate on * * Maintain clk-regmap clks list for providers use. */ void devm_clk_regmap_list_node(struct device *dev, struct clk_regmap *rclk) { list_add(&rclk->list_node, &clk_regmap_list); } EXPORT_SYMBOL(devm_clk_regmap_list_node); int clk_runtime_get_regmap(struct clk_regmap *rclk) { int ret; Loading
drivers/clk/qcom/clk-regmap.h +1 −0 Original line number Diff line number Diff line Loading @@ -64,6 +64,7 @@ int clk_pre_change_regmap(struct clk_hw *hw, unsigned long cur_rate, int clk_post_change_regmap(struct clk_hw *hw, unsigned long old_rate, unsigned long cur_rate); int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk); void devm_clk_regmap_list_node(struct device *dev, struct clk_regmap *rclk); bool clk_is_regmap_clk(struct clk_hw *hw); Loading