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Commit d7293b4f authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-alpha-pll: Replace hw->init in PLL code 



The hw->init is no longer valid after the HW clock is registered with
the clock framework, thus clean up the clock enable/disable. While at it
update the list register offset.

Change-Id: I965cd1d5c14efd2bea8cc220f2b19ed1f3ddfb8c
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 456857a0

drivers/clk/qcom/clk-alpha-pll.c

+6 −6
Original line number Diff line number Diff line
@@ -791,7 +791,7 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	 */

	if (is_enabled(&pll->clkr.hw) &&

	    !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))

		hw->init->ops->disable(hw);

		clk_alpha_pll_disable(hw);



	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
@@ -830,9 +830,9 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
		(pll->flags & SUPPORTS_DYNAMIC_UPDATE))

		clk_alpha_pll_dynamic_update(pll);



	if (is_enabled(&pll->clkr.hw) &&

	if (!is_enabled(&pll->clkr.hw) &&

		!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))

		hw->init->ops->enable(hw);

		clk_alpha_pll_enable(hw);



	return clk_alpha_pll_update_latch(pll, is_enabled);

}
@@ -1763,8 +1763,8 @@ static void clk_alpha_pll_list_registers(struct seq_file *f, struct clk_hw *hw) 
	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,

					&val);

		regmap_read(pll->clkr.regmap, pll->offset +

				pll->regs[data[i].offset], &val);

		clock_debug_output(f, "%20s: 0x%.8x\n", data[i].name, val);

	}
@@ -4411,7 +4411,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw) 




	pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n",

				hw->init->name, clk_hw_get_rate(hw), freq_hz);

			clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz);



	/* Setup the PLL for the new frequency */

	a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);