Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a9bc3390 authored by Tariq Toukan's avatar Tariq Toukan Committed by Saeed Mahameed
Browse files

net/mlx5e: kTLS, Fix progress params context WQE layout 



The TLS progress params context WQE should not include an
Eth segment, drop it.
In addition, align the tls_progress_params layout with the
HW specification document:
- fix the tisn field name.
- remove the valid bit.

Fixes: a12ff35e ("net/mlx5: Introduce TLS TX offload hardware bits and structures")
Fixes: d2ead1f3 ("net/mlx5e: Add kTLS TX HW offload support")
Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 26149e3e

drivers/net/ethernet/mellanox/mlx5/core/en.h

+7 −2
Original line number Diff line number Diff line
@@ -184,9 +184,14 @@ static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 


struct mlx5e_tx_wqe {

	struct mlx5_wqe_ctrl_seg ctrl;

	union {

		struct {

			struct mlx5_wqe_eth_seg  eth;

			struct mlx5_wqe_data_seg data[0];

		};

		u8 tls_progress_params_ctx[0];

	};

};



struct mlx5e_rx_wqe_ll {

	struct mlx5_wqe_srq_next_seg  next;

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.h

+4 −2
Original line number Diff line number Diff line
@@ -11,12 +11,14 @@ 
#include "accel/tls.h"



#define MLX5E_KTLS_STATIC_UMR_WQE_SZ \

	(sizeof(struct mlx5e_umr_wqe) + MLX5_ST_SZ_BYTES(tls_static_params))

	(offsetof(struct mlx5e_umr_wqe, tls_static_params_ctx) + \

	 MLX5_ST_SZ_BYTES(tls_static_params))

#define MLX5E_KTLS_STATIC_WQEBBS \

	(DIV_ROUND_UP(MLX5E_KTLS_STATIC_UMR_WQE_SZ, MLX5_SEND_WQE_BB))



#define MLX5E_KTLS_PROGRESS_WQE_SZ \

	(sizeof(struct mlx5e_tx_wqe) + MLX5_ST_SZ_BYTES(tls_progress_params))

	(offsetof(struct mlx5e_tx_wqe, tls_progress_params_ctx) + \

	 MLX5_ST_SZ_BYTES(tls_progress_params))

#define MLX5E_KTLS_PROGRESS_WQEBBS \

	(DIV_ROUND_UP(MLX5E_KTLS_PROGRESS_WQE_SZ, MLX5_SEND_WQE_BB))

#define MLX5E_KTLS_MAX_DUMP_WQEBBS 2

drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_tx.c

+2 −2
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ build_static_params(struct mlx5e_umr_wqe *wqe, u16 pc, u32 sqn, 
static void

fill_progress_params_ctx(void *ctx, struct mlx5e_ktls_offload_context_tx *priv_tx)

{

	MLX5_SET(tls_progress_params, ctx, pd, priv_tx->tisn);

	MLX5_SET(tls_progress_params, ctx, tisn, priv_tx->tisn);

	MLX5_SET(tls_progress_params, ctx, record_tracker_state,

		 MLX5E_TLS_PROGRESS_PARAMS_RECORD_TRACKER_STATE_START);

	MLX5_SET(tls_progress_params, ctx, auth_state,
@@ -104,7 +104,7 @@ build_progress_params(struct mlx5e_tx_wqe *wqe, u16 pc, u32 sqn, 
					     PROGRESS_PARAMS_DS_CNT);

	cseg->fm_ce_se         = fence ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;



	fill_progress_params_ctx(wqe->data, priv_tx);

	fill_progress_params_ctx(wqe->tls_progress_params_ctx, priv_tx);

}



static void tx_fill_wi(struct mlx5e_txqsq *sq,

include/linux/mlx5/mlx5_ifc.h

+2 −3
Original line number Diff line number Diff line
@@ -10054,9 +10054,8 @@ struct mlx5_ifc_tls_static_params_bits { 
};



struct mlx5_ifc_tls_progress_params_bits {

	u8         valid[0x1];

	u8         reserved_at_1[0x7];

	u8         pd[0x18];

	u8         reserved_at_0[0x8];

	u8         tisn[0x18];



	u8         next_record_tcp_sn[0x20];