Loading qcom/lahaina.dtsi +8 −3 Original line number Diff line number Diff line Loading @@ -537,9 +537,14 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { compatible = "qcom,dummycc"; clock-output-names = "videocc_clocks"; clock_videocc: qcom,videocc@abf0000 { compatible = "qcom,lahaina-videocc", "syscon"; reg = <0xabf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/lahaina.dtsi +8 −3 Original line number Diff line number Diff line Loading @@ -537,9 +537,14 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { compatible = "qcom,dummycc"; clock-output-names = "videocc_clocks"; clock_videocc: qcom,videocc@abf0000 { compatible = "qcom,lahaina-videocc", "syscon"; reg = <0xabf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading