Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a68d09a1 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUs 



The TLB handlers cannot handle this case, so disable it for now.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7007/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8a837cdb

arch/mips/include/asm/cpu-features.h

+8 −1
Original line number Diff line number Diff line
@@ -110,9 +110,15 @@ 
#ifndef cpu_has_smartmips

#define cpu_has_smartmips	(cpu_data[0].ases & MIPS_ASE_SMARTMIPS)

#endif



#ifndef cpu_has_rixi

# ifdef CONFIG_64BIT

# define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)

# else /* CONFIG_32BIT */

# define cpu_has_rixi		((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)

# endif

#endif



#ifndef cpu_has_mmips

# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS

#  define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
@@ -120,6 +126,7 @@ 
#  define cpu_has_mmips		0

# endif

#endif



#ifndef cpu_has_vtag_icache

#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)

#endif