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Commit a572ba63 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull core irq updates from Thomas Gleixner:
 "Updates from the irq departement:

   - Update the interrupt spreading code so it handles numa node with
     different CPU counts properly.

   - A large overhaul of the ARM GiCv3 driver to support new PPI and SPI
     ranges.

   - Conversion of all alloc_fwnode() users to use physical addresses
     instead of virtual addresses so the virtual addresses are not
     leaked. The physical address is sufficient to identify the
     associated interrupt chip.

   - Add support for Marvel MMP3, Amlogic Meson SM1 interrupt chips.

   - Enforce interrupt threading at compile time if RT is enabled.

   - Small updates and improvements all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  irqchip/gic-v3-its: Fix LPI release for Multi-MSI devices
  irqchip/uniphier-aidet: Use devm_platform_ioremap_resource()
  irqdomain: Add the missing assignment of domain->fwnode for named fwnode
  irqchip/mmp: Coexist with GIC root IRQ controller
  irqchip/mmp: Mask off interrupts from other cores
  irqchip/mmp: Add missing chained_irq_{enter,exit}()
  irqchip/mmp: Do not use of_address_to_resource() to get mux regs
  irqchip/meson-gpio: Add support for meson sm1 SoCs
  dt-bindings: interrupt-controller: New binding for the meson sm1 SoCs
  genirq/affinity: Remove const qualifier from node_to_cpumask argument
  genirq/affinity: Spread vectors on node according to nr_cpu ratio
  genirq/affinity: Improve __irq_build_affinity_masks()
  irqchip: Remove dev_err() usage after platform_get_irq()
  irqchip: Add include guard to irq-partition-percpu.h
  irqchip/mmp: Do not call irq_set_default_host() on DT platforms
  irqchip/gic-v3-its: Remove the redundant set_bit for lpi_map
  irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803
  irqchip/gic: Skip DT quirks when evaluating IIDR-based quirks
  irqchip/gic-v3: Warn about inconsistent implementations of extended ranges
  irqchip/gic-v3: Add EPPI range support
  ...
parents 258b16ec 9cc5b7fb

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -115,6 +115,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip0{6,7}       | #161010803      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ Required properties: 
    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)

    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)

    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)

    "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

+4 −2
Original line number Diff line number Diff line
@@ -44,11 +44,13 @@ properties: 
      be at least 4.



      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI

      interrupts. Other values are reserved for future use.

      interrupts, 2 for interrupts in the Extended SPI range, 3 for the

      Extended PPI range. Other values are reserved for future use.



      The 2nd cell contains the interrupt number for the interrupt type.

      SPI interrupts are in the range [0-987]. PPI interrupts are in the

      range [0-15].

      range [0-15]. Extented SPI interrupts are in the range [0-1023].

      Extended PPI interrupts are in the range [0-127].



      The 3rd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.

arch/arm/mach-mmp/regs-icu.h

+3 −0
Original line number Diff line number Diff line
@@ -11,6 +11,9 @@ 
#define ICU_VIRT_BASE	(AXI_VIRT_BASE + 0x82000)

#define ICU_REG(x)	(ICU_VIRT_BASE + (x))



#define ICU2_VIRT_BASE	(AXI_VIRT_BASE + 0x84000)

#define ICU2_REG(x)	(ICU2_VIRT_BASE + (x))



#define ICU_INT_CONF(n)		ICU_REG((n) << 2)

#define ICU_INT_CONF_MASK	(0xf)

drivers/irqchip/irq-gic-common.c

+19 −16
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, 
		void *data)

{

	for (; quirks->desc; quirks++) {

		if (quirks->compatible)

			continue;

		if (quirks->iidr != (quirks->mask & iidr))

			continue;

		if (quirks->init(data))
@@ -63,7 +65,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
	 * for "irq", depending on "type".

	 */

	raw_spin_lock_irqsave(&irq_controller_lock, flags);

	val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);

	val = oldval = readl_relaxed(base + confoff);

	if (type & IRQ_TYPE_LEVEL_MASK)

		val &= ~confmask;

	else if (type & IRQ_TYPE_EDGE_BOTH)
@@ -83,14 +85,10 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
	 * does not allow us to set the configuration or we are in a

	 * non-secure mode, and hence it may not be catastrophic.

	 */

	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);

	if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {

		if (WARN_ON(irq >= 32))

	writel_relaxed(val, base + confoff);

	if (readl_relaxed(base + confoff) != val)

		ret = -EINVAL;

		else

			pr_warn("GIC: PPI%d is secure or misconfigured\n",

				irq - 16);

	}



	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);



	if (sync_access)
@@ -132,26 +130,31 @@ void gic_dist_config(void __iomem *base, int gic_irqs, 
		sync_access();

}



void gic_cpu_config(void __iomem *base, void (*sync_access)(void))

void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))

{

	int i;



	/*

	 * Deal with the banked PPI and SGI interrupts - disable all

	 * PPI interrupts, ensure all SGI interrupts are enabled.

	 * Make sure everything is deactivated.

	 * private interrupts. Make sure everything is deactivated.

	 */

	writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);

	writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);

	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);

	for (i = 0; i < nr; i += 32) {

		writel_relaxed(GICD_INT_EN_CLR_X32,

			       base + GIC_DIST_ACTIVE_CLEAR + i / 8);

		writel_relaxed(GICD_INT_EN_CLR_X32,

			       base + GIC_DIST_ENABLE_CLEAR + i / 8);

	}



	/*

	 * Set priority on PPI and SGI interrupts

	 */

	for (i = 0; i < 32; i += 4)

	for (i = 0; i < nr; i += 4)

		writel_relaxed(GICD_INT_DEF_PRI_X4,

					base + GIC_DIST_PRI + i * 4 / 4);



	/* Ensure all SGI interrupts are now enabled */

	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);



	if (sync_access)

		sync_access();

}