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Commit 9cc5b7fb authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-5.4' of... 

Merge tag 'irqchip-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for Linux 5.4 from Marc Zyngier:

 - Large GICv3 updates to support new PPI and SPI ranges
 - Conver all alloc_fwnode() users to use PAs instead of VAs
 - Add support for Marvell's MMP3 irqchip
 - Add support for Amlogic Meson SM1
 - Various cleanups and fixes
parents 101f85b5 c9c96e30

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -115,6 +115,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip0{6,7}       | #161010803      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

+1 −0
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@@ -16,6 +16,7 @@ Required properties: 
    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)

    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)

    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)

    "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

+4 −2
Original line number Diff line number Diff line
@@ -44,11 +44,13 @@ properties: 
      be at least 4.



      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI

      interrupts. Other values are reserved for future use.

      interrupts, 2 for interrupts in the Extended SPI range, 3 for the

      Extended PPI range. Other values are reserved for future use.



      The 2nd cell contains the interrupt number for the interrupt type.

      SPI interrupts are in the range [0-987]. PPI interrupts are in the

      range [0-15].

      range [0-15]. Extented SPI interrupts are in the range [0-1023].

      Extended PPI interrupts are in the range [0-127].



      The 3rd cell is the flags, encoded as follows:

      bits[3:0] trigger type and level flags.

arch/arm/mach-mmp/regs-icu.h

+3 −0
Original line number Diff line number Diff line
@@ -11,6 +11,9 @@ 
#define ICU_VIRT_BASE	(AXI_VIRT_BASE + 0x82000)

#define ICU_REG(x)	(ICU_VIRT_BASE + (x))



#define ICU2_VIRT_BASE	(AXI_VIRT_BASE + 0x84000)

#define ICU2_REG(x)	(ICU2_VIRT_BASE + (x))



#define ICU_INT_CONF(n)		ICU_REG((n) << 2)

#define ICU_INT_CONF_MASK	(0xf)

drivers/gpio/gpio-ixp4xx.c

+1 −1
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@@ -400,7 +400,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) 
		g->fwnode = of_node_to_fwnode(np);

	} else {

		parent = ixp4xx_get_irq_domain();

		g->fwnode = irq_domain_alloc_fwnode(g->base);

		g->fwnode = irq_domain_alloc_fwnode(&res->start);

		if (!g->fwnode) {

			dev_err(dev, "no domain base\n");

			return -ENODEV;