disp: msm: sde: avoid ctl_reset during display disable sequence

When SW writes to the CTL_SW_RESET register, the hardware
enters a sequence to stop pending OTs and once that’s done
it asserts sw_reset to that CTL path for exactly 100 mdp_clks.
This is hardcoded in the HW design for many generations. The
sw_reset propagates to all the MDP hardware blocks on mdp_clk
and pixel_clk. When the mdpclk : pclk ratio is greater than 100
mdp_clk pulse isn’t long enough to reset the read side. So,
the async FIFO (i.e. the hardware responsible to transfer pixels
from mdp_clk to pixel_clk) only gets partially reset. The mdp_clk
side is reset but the pixel_clk side does NOT. The async FIFO is
in a bad state and believes there’s data in the FIFO. At this
point, the "valid" sent to DSI controller gets flatlined high
and DSI believes transfers are initiated eventually leading
to underflow once panel commands are initiated.

Add changes in software sequence to avoid triggering ctl_reset
to due to above HW limitation.

Change-Id: Iae44dba6ef59cbd5869a7f336af5dd38f93eafdd
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>