msm: gsi: cache last 20 gsi interrupt for interrupt storm debug

GSI interrupt storm can happen due to un-clocked gsi isr.
If we enable clock and assert, there is a chance the gsi isr will
be already handled.
To debug it further, the change is to cache last 20 gsi isr with
timestamp.

Change-Id: I30be03a20df9f11be7f5d8c06b049591305940bb
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>