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Commit a0cdef9e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/uvd6: add bypass support for fiji (v3) 



Handle uvd clock bypass settings as part of clockgating
setup.

v2: fix gate logic
v3: fix header include

Reviewed-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bdf1ecea

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+19 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#include "uvd/uvd_6_0_sh_mask.h"

#include "oss/oss_2_0_d.h"

#include "oss/oss_2_0_sh_mask.h"

#include "smu/smu_7_1_3_d.h"

#include "smu/smu_7_1_3_sh_mask.h"

#include "vi.h"



static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
@@ -823,6 +825,20 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 
}

#endif



static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);



	if (enable)

		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);

	else

		tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |

			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);



	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);

}



static int uvd_v6_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{
@@ -830,6 +846,9 @@ static int uvd_v6_0_set_clockgating_state(void *handle, 
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	static int curstate = -1;



	if (adev->asic_type == CHIP_FIJI)

		uvd_v6_set_bypass_mode(adev, enable);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

		return 0;