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Commit bdf1ecea authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) 



Need to call the IP cg callbacks.

v2: fix gate logic

Reviewed-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce90dbd9

drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c

+9 −2
Original line number Diff line number Diff line
@@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 


	data->uvd_power_gated = bgate;



	if (bgate)

	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

					  AMD_IP_BLOCK_TYPE_UVD,

					  AMD_CG_STATE_GATE);

		fiji_update_uvd_dpm(hwmgr, true);

	else

	} else {

		fiji_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

					  AMD_IP_BLOCK_TYPE_UVD,

					  AMD_PG_STATE_UNGATE);

	}



	return 0;

}