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Commit a076a286 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: Add all clock controller and gdsc nodes for scshrike 

Add support for aopcc, camcc, dispcc, gcc, gpucc, npucc,
rpmhcc, scc, videocc, debugcc and also add gdsc regulators.

Change-Id: Ia5751e7de691e3da606c4e2b94f21e726830d0f1
parent ee580336

qcom/sa8195-gdsc.dtsi

0 → 100644
+47 −0
Original line number Diff line number Diff line 
#include "sm8150-gdsc.dtsi"



&soc {

	/* GDSCs in Global CC */

	pcie_2_gdsc: qcom,gdsc@19d004 {

		compatible = "qcom,gdsc";

		reg = <0x19d004 0x4>;

		regulator-name = "pcie_2_gdsc";

		status = "disabled";

	};



	pcie_3_gdsc: qcom,gdsc@1a3004 {

		compatible = "qcom,gdsc";

		reg = <0x1a3004 0x4>;

		regulator-name = "pcie_3_gdsc";

		status = "disabled";

	};



	ufs_card_2_gdsc: qcom,gdsc@1a2004 {

		compatible = "qcom,gdsc";

		reg = <0x1a2004 0x4>;

		regulator-name = "ufs_card_2_gdsc";

		status = "disabled";

	};



	usb30_mp_gdsc: qcom,gdsc@1a6004 {

		compatible = "qcom,gdsc";

		reg = <0x1a6004 0x4>;

		regulator-name = "usb30_mp_gdsc";

		status = "disabled";

	};



	/* GDSCs in Camera CC */

	ife_2_gdsc: qcom,gdsc@ad0f004 {

		compatible = "qcom,gdsc";

		reg = <0xad0f004 0x4>;

		regulator-name = "ife_2_gdsc";

		status = "disabled";

	};



	ife_3_gdsc: qcom,gdsc@ad0f070 {

		compatible = "qcom,gdsc";

		reg = <0xad0f070 0x4>;

		regulator-name = "ife_3_gdsc";

		status = "disabled";

	};

};

qcom/sa8195-pmic.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -59,4 +59,13 @@ 
	/delete-node/ refgen;

};



&camcc {

	vdd_mx-supply = <&VDD_MX_LEVEL>;

	vdd_mm-supply = <&VDD_MMCX_LEVEL>;

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_MMCX_LEVEL>;

};



#include "sa8195p-regulator.dtsi"

qcom/sa8195p.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -7,3 +7,7 @@ 
	qcom,msm-id = <405 0x20000>;

};



&scc {

	vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>;

	status = "ok";

};

qcom/sdmshrike-v2.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -6,3 +6,28 @@ 
	qcom,msm-id = <340 0x20000>;

};



/delete-node/ &ufs_card_gdsc;



&camcc {

	compatible = "qcom,scshrike-camcc-v2", "syscon";

};



&dispcc {

	compatible = "qcom,scshrike-dispcc-v2", "syscon";

};



&gcc {

	compatible = "qcom,scshrike-gcc-v2", "syscon";

};



&npucc {

	compatible = "qcom,sm8150-npucc-v2", "syscon";

};



&scc {

	compatible = "qcom,sa8195-scc-v2", "syscon";

};



&videocc {

	compatible = "qcom,sm8150-videocc-v2", "syscon";

};

qcom/sdmshrike.dtsi

+361 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/clock/qcom,camcc-scshrike.h>

#include <dt-bindings/clock/qcom,dispcc-scshrike.h>

#include <dt-bindings/clock/qcom,gcc-scshrike.h>

#include <dt-bindings/clock/qcom,gpucc-sm8150.h>

#include <dt-bindings/clock/qcom,npucc-sm8150.h>

#include <dt-bindings/clock/qcom,scc-sm8150.h>

#include <dt-bindings/clock/qcom,videocc-sm8150.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/interconnect/qcom,icc.h>

#include <dt-bindings/interconnect/qcom,scshrike.h>
@@ -579,6 +587,22 @@ 
		};

	};



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <38400000>;

			clock-output-names = "xo_board";

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32000>;

			clock-output-names = "sleep_clk";

		};

	};



	qcom,msm-imem@146bf000 {

		compatible = "qcom,msm-imem";

		reg = <0x146bf000 0x1000>;
@@ -654,6 +678,12 @@ 
			compatible = "qcom,bcm-voter";

		};



		rpmhcc: clock-controller {

			compatible = "qcom,sm8150-rpmh-clk";

			#clock-cells = <1>;

			status = "okay";

		};



		system_pm {

			compatible = "qcom,system-pm";

		};
@@ -777,6 +807,147 @@ 
		#mbox-cells = <1>;

	};



	aopcc: qcom,aopcc@0 {

		compatible = "qcom,aop-qmp-clk";

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

		#clock-cells = <1>;

	};



	gcc: clock-controller@100000 {

		compatible = "qcom,scshrike-gcc", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&rpmhcc RPMH_CXO_CLK_A>,

			<&sleep_clk>;

		clock-names =

			"bi_tcxo",

			"bi_tcxo_ao",

			"sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	scc: clock-controller@2b10000 {

		compatible = "qcom,sa8195-scc";

		reg = <0x2b10000 0x30000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "bi_tcxo";

		#clock-cells = <1>;

		status = "disabled";

	};



	gpucc: clock-controller@2c90000 {

		compatible = "qcom,scshrike-gpucc", "syscon";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_GPU_GPLL0_CLK_SRC>,

			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

		clock-names = "bi_tcxo",

			"gcc_gpu_gpll0_clk_src",

			"gcc_gpu_gpll0_div_clk_src";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	npucc: clock-controller@9910000 {

		compatible = "qcom,sm8150-npucc", "syscon";

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_gdsc-supply = <&npu_core_gdsc>;

		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,

			<&gcc GCC_NPU_GPLL0_CLK_SRC>,

			<&gcc GCC_NPU_AXI_CLK>;

		clock-names =

			"bi_tcxo",

			"gcc_npu_gpll0_div_clk_src",

			"gcc_npu_gpll0_clk_src",

			"gcc_npu_axi_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	videocc: clock-controller@ab00000 {

		compatible = "qcom,sm8150-videocc", "syscon";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clocks = <&gcc GCC_VIDEO_AHB_CLK>,

			<&rpmhcc RPMH_CXO_CLK>;

		clock-names =

			"cfg_ahb_clk",

			"bi_tcxo";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	camcc: clock-controller@ad00000 {

		compatible = "qcom,scshrike-camcc", "syscon";

		reg = <0xad00000 0x20000>;

		reg-name = "cc_base";

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		clocks = <&gcc GCC_CAMERA_AHB_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&sleep_clk>;

		clock-names =

			"cfg_ahb_clk",

			"bi_tcxo",

			"sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: clock-controller@af00000 {

		compatible = "qcom,scshrike-dispcc", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clocks = <&gcc GCC_DISP_AHB_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&sleep_clk>;

		clock-names =

			"cfg_ahb_clk",

			"bi_tcxo",

			"sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	apsscc: syscon@182a0000 {

		compatible = "syscon";

		reg = <0x182a0000 0x1c>;

	};



	mccc: syscon@90b0000 {

		compatible = "syscon";

		reg = <0x90b0000 0x54>;

	};



	debugcc: debug-clock-controller@0 {

		compatible = "qcom,scshrike-debugcc";

		qcom,gcc = <&gcc>;

		qcom,videocc = <&videocc>;

		qcom,camcc = <&camcc>;

		qcom,dispcc = <&dispcc>;

		qcom,npucc = <&npucc>;

		qcom,gpucc = <&gpucc>;

		qcom,apsscc = <&apsscc>;

		qcom,mccc = <&mccc>;

		clock-names = "xo_clk_src";

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		#clock-cells = <1>;

	};



	tcsr_mutex_block: syscon@1f40000 {

		compatible = "syscon";

		reg = <0x1f40000 0x20000>;
@@ -1077,3 +1248,193 @@ 
#include "sa8195-regulator.dtsi"

#include "sm8150-pm.dtsi"

#include "sa8195-smp2p.dtsi"

#include "sa8195-gdsc.dtsi"



&emac_gdsc {

	status = "ok";

};



&pcie_0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&pcie_1_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&pcie_2_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&pcie_3_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&ufs_card_2_gdsc {

	status = "ok";

};



&ufs_card_gdsc {

	status = "ok";

};



&ufs_phy_gdsc {

	status = "ok";

};



&usb30_mp_gdsc {

	status = "ok";

};



&usb30_prim_gdsc {

	status = "ok";

};



&usb30_sec_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu0_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu1_gdsc {

	status = "ok";

};



&bps_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&ife_0_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};



&ife_1_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};



&ife_2_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};



&ife_3_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};



&ipe_0_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&ipe_1_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&titan_top_gdsc {

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};



&mdss_core_gdsc {

	clocks = <&gcc GCC_DISP_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&gpu_cx_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	parent-supply = <&VDD_GFX_LEVEL>;

	status = "ok";

};



&npu_core_gdsc {

	clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;

	clock-names = "ahb_clk";

	status = "ok";

};



&mvs0_gdsc {

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&mvs1_gdsc {

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	qcom,support-hw-trigger;

	status = "ok";

};



&mvsc_gdsc {

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	clock-names = "ahb_clk";

	parent-supply = <&VDD_MMCX_LEVEL>;

	status = "ok";

};