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Commit 9f50810d authored by Aditya Bavanari's avatar Aditya Bavanari Committed by Gerrit - the friendly Code Review server
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asoc: codecs: Update rouleur watchdog interrupt sequence



Update PDM watchdog interrupt sequence for rouleur
codec. Add HPH PA gain registers in regmap and update
defaults. Update mic bias register bits and rouleur
version for ADIE RTC to work.

Change-Id: I1bbb41efcdd9a0a8b38fcd4beadbd5d639a4b858
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent e7efdae3
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+1 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static struct wcd_mbhc_register
	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
			  ROULEUR_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
	WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
			  ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x04, 2, 0),
			  ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x06, 1, 0),
	WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
			  SND_SOC_NOPM, 0x00, 0, 0),
	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
+2 −0
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ static const struct reg_default rouleur_defaults[] = {
	{ ROULEUR_ANA_HPHPA_CNP_CTL_2,            0x2B },
	{ ROULEUR_ANA_HPHPA_PA_STATUS,            0x00 },
	{ ROULEUR_ANA_HPHPA_FSM_CLK,              0x12 },
	{ ROULEUR_ANA_HPHPA_L_GAIN,               0x00 },
	{ ROULEUR_ANA_HPHPA_R_GAIN,               0x00 },
	{ ROULEUR_SWR_HPHPA_HD2,                  0x1B },
	{ ROULEUR_ANA_HPHPA_SPARE_CTL,            0x02 },
	{ ROULEUR_ANA_SURGE_EN,                   0x38 },
+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ const u8 rouleur_reg_access_analog[ROULEUR_REG(
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG,
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_L_GAIN)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_R_GAIN)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG,
	[ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG,
+28 −45
Original line number Diff line number Diff line
@@ -475,14 +475,8 @@ static int rouleur_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
				0x04, 0x04);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x01, 0x01);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component,
			ROULEUR_DIG_SWR_PDM_WD_CTL0,
			0x03, 0x00);
		snd_soc_component_update_bits(component,
			ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
			0x01, 0x00);
@@ -546,14 +540,8 @@ static int rouleur_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
				0x08, 0x08);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x02);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL1,
				0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component,
			ROULEUR_DIG_SWR_PDM_WD_CTL1,
			0x03, 0x00);
		snd_soc_component_update_bits(component,
			ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x00);
		break;
@@ -582,18 +570,12 @@ static int rouleur_codec_ear_lo_dac_event(struct snd_soc_dapm_widget *w,
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
				0x01, 0x01);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x03);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL,
				0x04, 0x04);

		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x00);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
				0x01, 0x00);
@@ -622,14 +604,11 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
				    rouleur->rx_swr_dev->dev_num,
				    true);

		snd_soc_component_update_bits(component,
					ROULEUR_ANA_HPHPA_CNP_CTL_2,
					0x40, 0x40);
		set_bit(HPH_PA_DELAY, &rouleur->status_mask);
		/* TODO: WHY SECOND TIME */
		ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
					    rouleur->rx_swr_dev->dev_num,
					    true);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
			ROULEUR_DIG_SWR_PDM_WD_CTL1,
			0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMU:
		/*
@@ -676,8 +655,8 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
					     WCD_EVENT_POST_HPHR_PA_OFF,
					     &rouleur->mbhc->wcd_mbhc);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_HPHPA_CNP_CTL_2,
				0x40, 0x00);
				ROULEUR_DIG_SWR_PDM_WD_CTL1,
				0x03, 0x00);
		break;
	};
	return ret;
@@ -700,10 +679,11 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
		ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
				    rouleur->rx_swr_dev->dev_num,
				    true);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_HPHPA_CNP_CTL_2,
				0x80, 0x80);
		set_bit(HPH_PA_DELAY, &rouleur->status_mask);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMU:
		/*
@@ -748,8 +728,8 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
					     WCD_EVENT_POST_HPHL_PA_OFF,
					     &rouleur->mbhc->wcd_mbhc);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_HPHPA_CNP_CTL_2,
				0x80, 0x00);
			ROULEUR_DIG_SWR_PDM_WD_CTL0,
			0x03, 0x00);

		break;
	};
@@ -773,10 +753,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
		ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
			    rouleur->rx_swr_dev->dev_num,
			    true);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x80, 0x80);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMU:
		if (rouleur->update_wcd_event)
@@ -795,10 +775,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
						(WCD_RX1 << 0x10 | 0x1));
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x80, 0x00);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x00);
	};
	return ret;
}
@@ -823,10 +803,10 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x40, 0x40);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x80, 0x80);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x03);
		break;
	case SND_SOC_DAPM_POST_PMU:
		if (rouleur->update_wcd_event)
@@ -845,13 +825,13 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
						(WCD_RX1 << 0x10 | 0x1));
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x80, 0x00);
		snd_soc_component_update_bits(component,
				ROULEUR_ANA_COMBOPA_CTL,
				0x40, 0x00);
		usleep_range(5000, 5100);
		snd_soc_component_update_bits(component,
				ROULEUR_DIG_SWR_PDM_WD_CTL0,
				0x03, 0x00);
	};
	return ret;
}
@@ -1552,6 +1532,9 @@ static int rouleur_codec_enable_pa_vpos(struct snd_soc_dapm_widget *w,
		break;
	case SND_SOC_DAPM_POST_PMD:
		set_bit(ALLOW_VPOS_DISABLE, &rouleur->status_mask);
		ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
				rouleur->rx_swr_dev->dev_num,
				false);
		break;
	}
	return 0;
@@ -1822,7 +1805,7 @@ static ssize_t rouleur_version_read(struct snd_info_entry *entry,

	switch (priv->version) {
	case ROULEUR_VERSION_1_0:
		len = snprintf(buffer, sizeof(buffer), "rouleur_1_0\n");
		len = snprintf(buffer, sizeof(buffer), "ROULEUR_1_0\n");
		break;
	default:
		len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");