Loading asoc/lahaina-port-config.h +27 −40 Original line number Diff line number Diff line Loading @@ -11,50 +11,44 @@ #define WSA_MSTR_PORT_MASK 0xFF /* * Add port configuration in the format *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl} *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir, * stream_type} */ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = { {7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF}, {7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF}, {15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, }; static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, {7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, }; static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0}, {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, }; /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX2 */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */ /* Headset + PCM Haptics */ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */ {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */ {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */ {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */ {0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */ }; /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_v2[SWR_MSTR_PORT_LEN] = { {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},/* PCM OUT */ {1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1}, /* TX1 */ {1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX2 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX4 */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; static struct swr_mstr_port_map sm_port_map[] = { Loading @@ -64,11 +58,4 @@ static struct swr_mstr_port_map sm_port_map[] = { {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, }; static struct swr_mstr_port_map sm_port_map_v2[] = { {TX_MACRO, SWR_UC0, tx_frame_params_v2}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, }; #endif /* _LAHAINA_PORT_CONFIG */ asoc/lahaina.c +46 −0 Original line number Diff line number Diff line Loading @@ -142,6 +142,7 @@ enum { RX_CDC_DMA_RX_2, RX_CDC_DMA_RX_3, RX_CDC_DMA_RX_5, RX_CDC_DMA_RX_6, CDC_DMA_RX_MAX, }; Loading Loading @@ -634,6 +635,7 @@ static struct dev_config cdc_dma_rx_cfg[] = { [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, }; /* Default configuration of Codec DMA Interface TX */ Loading Loading @@ -776,6 +778,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text); Loading Loading @@ -824,6 +827,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text) static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate, Loading @@ -834,12 +838,15 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_sample_rate, cdc80_dma_sample_rate_text); /* WCD9385 */ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate, Loading @@ -850,6 +857,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text); static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text); Loading Loading @@ -2757,6 +2766,9 @@ static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol) else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5", sizeof("RX_CDC_DMA_RX_5"))) idx = RX_CDC_DMA_RX_5; else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_6", sizeof("RX_CDC_DMA_RX_6"))) idx = RX_CDC_DMA_RX_6; else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0", sizeof("WSA_CDC_DMA_TX_0"))) idx = WSA_CDC_DMA_TX_0; Loading Loading @@ -3288,6 +3300,9 @@ static int msm_cdc_dma_get_idx_from_beid(int32_t be_id) case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5: idx = RX_CDC_DMA_RX_5; break; case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: idx = RX_CDC_DMA_RX_6; break; case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0: idx = TX_CDC_DMA_TX_0; break; Loading Loading @@ -3527,6 +3542,8 @@ static const struct snd_kcontrol_new msm_int_snd_controls[] = { cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Channels", rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_get, cdc_dma_tx_ch_put), SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs, Loading Loading @@ -3622,6 +3639,8 @@ static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = { cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc80_dma_rx_6_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate", rx_cdc80_dma_rx_0_sample_rate, cdc_dma_rx_sample_rate_get, Loading @@ -3642,6 +3661,10 @@ static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = { rx_cdc80_dma_rx_5_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate", rx_cdc80_dma_rx_6_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), }; static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { Loading @@ -3655,6 +3678,8 @@ static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc85_dma_rx_6_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate", rx_cdc85_dma_rx_0_sample_rate, cdc_dma_rx_sample_rate_get, Loading @@ -3675,6 +3700,10 @@ static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { rx_cdc85_dma_rx_5_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate", rx_cdc85_dma_rx_6_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), }; static const struct snd_kcontrol_new msm_common_snd_controls[] = { Loading Loading @@ -4390,6 +4419,7 @@ static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: idx = msm_cdc_dma_get_idx_from_beid(dai_link->id); param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, cdc_dma_rx_cfg[idx].bit_format); Loading Loading @@ -4834,6 +4864,7 @@ static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream, case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: { ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id); pr_debug("%s: id %d rx_ch=%d\n", __func__, Loading Loading @@ -6643,6 +6674,21 @@ static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = { .ops = &msm_cdc_dma_be_ops, SND_SOC_DAILINK_REG(rx_dma_rx3), }, { .name = LPASS_BE_RX_CDC_DMA_RX_6, .stream_name = "RX CDC DMA6 Playback", #if IS_ENABLED(CONFIG_AUDIO_QGKI) .dynamic_be = 1, #endif /* CONFIG_AUDIO_QGKI */ .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, .be_hw_params_fixup = msm_be_hw_params_fixup, .ignore_pmdown_time = 1, .ignore_suspend = 1, .ops = &msm_cdc_dma_be_ops, SND_SOC_DAILINK_REG(rx_dma_rx6), }, /* TX CDC DMA Backend DAI Links */ { .name = LPASS_BE_TX_CDC_DMA_TX_3, Loading asoc/msm_dailink.h +6 −0 Original line number Diff line number Diff line Loading @@ -513,6 +513,12 @@ SND_SOC_DAILINK_DEFS(rx_dma_rx3, COMP_CODEC("wcd938x_codec", "wcd938x_cdc")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(rx_dma_rx6, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-cdc-dma-dev.45116")), DAILINK_COMP_ARRAY(COMP_CODEC("bolero_codec", "rx_macro_rx6"), COMP_CODEC("swr-haptics", "swr_haptics")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(tx_dma_tx3, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-cdc-dma-dev.45111")), DAILINK_COMP_ARRAY(COMP_CODEC("bolero_codec", "tx_macro_tx1"), Loading Loading
asoc/lahaina-port-config.h +27 −40 Original line number Diff line number Diff line Loading @@ -11,50 +11,44 @@ #define WSA_MSTR_PORT_MASK 0xFF /* * Add port configuration in the format *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl} *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir, * stream_type} */ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = { {7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF}, {7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF}, {15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, }; static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, {7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, }; static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0}, {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, }; /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX2 */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */ /* Headset + PCM Haptics */ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */ {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */ {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */ {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */ {0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */ }; /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_v2[SWR_MSTR_PORT_LEN] = { {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},/* PCM OUT */ {1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1}, /* TX1 */ {1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX2 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */ {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX4 */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */ {3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; static struct swr_mstr_port_map sm_port_map[] = { Loading @@ -64,11 +58,4 @@ static struct swr_mstr_port_map sm_port_map[] = { {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, }; static struct swr_mstr_port_map sm_port_map_v2[] = { {TX_MACRO, SWR_UC0, tx_frame_params_v2}, {RX_MACRO, SWR_UC0, rx_frame_params_default}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default}, }; #endif /* _LAHAINA_PORT_CONFIG */
asoc/lahaina.c +46 −0 Original line number Diff line number Diff line Loading @@ -142,6 +142,7 @@ enum { RX_CDC_DMA_RX_2, RX_CDC_DMA_RX_3, RX_CDC_DMA_RX_5, RX_CDC_DMA_RX_6, CDC_DMA_RX_MAX, }; Loading Loading @@ -634,6 +635,7 @@ static struct dev_config cdc_dma_rx_cfg[] = { [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, [RX_CDC_DMA_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, }; /* Default configuration of Codec DMA Interface TX */ Loading Loading @@ -776,6 +778,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text); Loading Loading @@ -824,6 +827,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_format, cdc80_bit_format_text) static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_2_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_format, cdc80_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_0_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_1_sample_rate, Loading @@ -834,12 +838,15 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_3_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_5_sample_rate, cdc80_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc80_dma_rx_6_sample_rate, cdc80_dma_sample_rate_text); /* WCD9385 */ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_2_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_format, bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_0_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_1_sample_rate, Loading @@ -850,6 +857,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_3_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_5_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc85_dma_rx_6_sample_rate, cdc_dma_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text); static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text); Loading Loading @@ -2757,6 +2766,9 @@ static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol) else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5", sizeof("RX_CDC_DMA_RX_5"))) idx = RX_CDC_DMA_RX_5; else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_6", sizeof("RX_CDC_DMA_RX_6"))) idx = RX_CDC_DMA_RX_6; else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0", sizeof("WSA_CDC_DMA_TX_0"))) idx = WSA_CDC_DMA_TX_0; Loading Loading @@ -3288,6 +3300,9 @@ static int msm_cdc_dma_get_idx_from_beid(int32_t be_id) case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5: idx = RX_CDC_DMA_RX_5; break; case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: idx = RX_CDC_DMA_RX_6; break; case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0: idx = TX_CDC_DMA_TX_0; break; Loading Loading @@ -3527,6 +3542,8 @@ static const struct snd_kcontrol_new msm_int_snd_controls[] = { cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Channels", rx_cdc_dma_rx_6_chs, cdc_dma_rx_ch_get, cdc_dma_rx_ch_put), SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_get, cdc_dma_tx_ch_put), SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs, Loading Loading @@ -3622,6 +3639,8 @@ static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = { cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc80_dma_rx_5_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc80_dma_rx_6_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate", rx_cdc80_dma_rx_0_sample_rate, cdc_dma_rx_sample_rate_get, Loading @@ -3642,6 +3661,10 @@ static const struct snd_kcontrol_new msm_int_wcd9380_snd_controls[] = { rx_cdc80_dma_rx_5_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate", rx_cdc80_dma_rx_6_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), }; static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { Loading @@ -3655,6 +3678,8 @@ static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc85_dma_rx_5_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 Format", rx_cdc85_dma_rx_6_format, cdc_dma_rx_format_get, cdc_dma_rx_format_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate", rx_cdc85_dma_rx_0_sample_rate, cdc_dma_rx_sample_rate_get, Loading @@ -3675,6 +3700,10 @@ static const struct snd_kcontrol_new msm_int_wcd9385_snd_controls[] = { rx_cdc85_dma_rx_5_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), SOC_ENUM_EXT("RX_CDC_DMA_RX_6 SampleRate", rx_cdc85_dma_rx_6_sample_rate, cdc_dma_rx_sample_rate_get, cdc_dma_rx_sample_rate_put), }; static const struct snd_kcontrol_new msm_common_snd_controls[] = { Loading Loading @@ -4390,6 +4419,7 @@ static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: idx = msm_cdc_dma_get_idx_from_beid(dai_link->id); param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, cdc_dma_rx_cfg[idx].bit_format); Loading Loading @@ -4834,6 +4864,7 @@ static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream, case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5: case MSM_BACKEND_DAI_RX_CDC_DMA_RX_6: { ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id); pr_debug("%s: id %d rx_ch=%d\n", __func__, Loading Loading @@ -6643,6 +6674,21 @@ static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = { .ops = &msm_cdc_dma_be_ops, SND_SOC_DAILINK_REG(rx_dma_rx3), }, { .name = LPASS_BE_RX_CDC_DMA_RX_6, .stream_name = "RX CDC DMA6 Playback", #if IS_ENABLED(CONFIG_AUDIO_QGKI) .dynamic_be = 1, #endif /* CONFIG_AUDIO_QGKI */ .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, .be_hw_params_fixup = msm_be_hw_params_fixup, .ignore_pmdown_time = 1, .ignore_suspend = 1, .ops = &msm_cdc_dma_be_ops, SND_SOC_DAILINK_REG(rx_dma_rx6), }, /* TX CDC DMA Backend DAI Links */ { .name = LPASS_BE_TX_CDC_DMA_TX_3, Loading
asoc/msm_dailink.h +6 −0 Original line number Diff line number Diff line Loading @@ -513,6 +513,12 @@ SND_SOC_DAILINK_DEFS(rx_dma_rx3, COMP_CODEC("wcd938x_codec", "wcd938x_cdc")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(rx_dma_rx6, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-cdc-dma-dev.45116")), DAILINK_COMP_ARRAY(COMP_CODEC("bolero_codec", "rx_macro_rx6"), COMP_CODEC("swr-haptics", "swr_haptics")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(tx_dma_tx3, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-cdc-dma-dev.45111")), DAILINK_COMP_ARRAY(COMP_CODEC("bolero_codec", "tx_macro_tx1"), Loading