mmc: core: Set the correct frequency when scaling down to DDR mode

When scaling down to DDR mode we are passing 52Mhz to mmc_set_clock.
The SDHC requires internal clock frequency to be double the actual clock
that will be set for DDR mode. The controller uses the faster
clock(100/400MHz) for some part of SDHC internal h/w logic and send
the actual required clock (50/200MHz) to the card.
So in sdhci_msm_set_clock we multiply the clock by 2 for DDR modes.

Finally when we set host clk rate to 104Mhz then it scales to the nearest
equal or larger value which is 192Mhz for sdcc1_apps clk as per clk
drivers.
High frequency of 192Mhz for DDR52 mode leads to CRC errors for some
targets.

Hence Set the frequency to 50Mhz instead of 52Mhz.

Change-Id: I1d536db1dec4dfe16f41fd66362819c6db362901
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>