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Commit 9edf908a authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: imx: add i.MX7ULP SoC revision support 



i.MX7ULP SoC's revision info is inside the SIM module,
bit[31:28] of JTAG_ID register defines revision as below
from B0:

0001        B0
0010        B1

This patch adds SoC revision support for i.MX7ULP, test
result as below:

root@imx7ulp-evk ~$ cat /sys/devices/soc0/revision
2.1

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6d45a402

arch/arm/mach-imx/mach-imx7ulp.c

+39 −0
Original line number Diff line number Diff line
@@ -6,18 +6,57 @@ 
 */



#include <linux/irqchip.h>

#include <linux/mfd/syscon.h>

#include <linux/of_platform.h>

#include <linux/regmap.h>

#include <asm/mach/arch.h>



#include "common.h"

#include "cpuidle.h"

#include "hardware.h"



#define SIM_JTAG_ID_REG		0x8c



static void __init imx7ulp_set_revision(void)

{

	struct regmap *sim;

	u32 revision;



	sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");

	if (IS_ERR(sim)) {

		pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");

		return;

	}



	if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {

		pr_warn("failed to read sim regmap!\n");

		return;

	}



	/*

	 * bit[31:28] of JTAG_ID register defines revision as below from B0:

	 * 0001        B0

	 * 0010        B1

	 */

	switch (revision >> 28) {

	case 1:

		imx_set_soc_revision(IMX_CHIP_REVISION_2_0);

		break;

	case 2:

		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);

		break;

	default:

		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);

		break;

	}

}



static void __init imx7ulp_init_machine(void)

{

	imx7ulp_pm_init();



	mxc_set_cpu_type(MXC_CPU_IMX7ULP);

	imx7ulp_set_revision();

	of_platform_default_populate(NULL, NULL, imx_soc_device_init());

}