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Commit 9ed837fb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update DISPCC and debugcc clock nodes for YUPIK"

parents 30fc64a2 b77c2fed

qcom/yupik-rumi.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -189,3 +189,12 @@ 
	clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;

	status = "disabled";

};



&dispcc {

	clocks = <&bi_tcxo>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,

		<&gcc GCC_DISP_AHB_CLK>;

};



&debugcc {

	clocks = <&bi_tcxo>;

};

qcom/yupik.dtsi

+31 −2
Original line number Diff line number Diff line
@@ -962,8 +962,13 @@ 
	};



	dispcc: clock-controller@af00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		compatible = "qcom,yupik-dispcc", "syscon";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,

		       <&gcc GCC_DISP_AHB_CLK>;

		clock-names = "bi_tcxo", "gcc_disp_gpll0_clk","cfg_ahb";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -994,6 +999,30 @@ 
		#reset-cells = <1>;

	};



	apsscc: syscon@182a0000 {

		compatible = "syscon";

		reg = <0x182a0000 0x1c>;

	};



	mccc: syscon@90ba000 {

		compatible = "syscon";

		reg = <0x90ba000 0x54>;

	};



	debugcc: debug-clock-controller@0 {

		compatible = "qcom,yupik-debugcc";

		qcom,gcc = <&gcc>;

		qcom,camcc = <&camcc>;

		qcom,dispcc = <&dispcc>;

		qcom,gpucc = <&gpucc>;

		qcom,videocc = <&videocc>;

		qcom,apsscc = <&apsscc>;

		qcom,mccc = <&mccc>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo_clk_src";

		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x18591000 0x1000>, <0x18592000 0x1000>,