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Commit 30fc64a2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add iommu and h/w reset support for yupik"

parents 89c79f74 fc340212

qcom/yupik.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -2546,6 +2546,10 @@ 
		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",

			    "cqhci_ice_hwkm";



		iommus = <&apps_smmu 0xc0 0x0>;

		dma-coherent;

		qcom,iommu-dma = "bypass";



		interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";
@@ -2591,6 +2595,8 @@ 
		mmc-hs400-1_8v;

		mmc-hs400-enhanced-strobe;



		cap-mmc-hw-reset;



		bus-width = <8>;

		non-removable;

		supports-cqe;
@@ -2598,6 +2604,10 @@ 
		qcom,devfreq,freq-table = <50000000 200000000>;

		qcom,scaling-lower-bus-speed-mode = "DDR52";



		/* Add dt entry for gcc hw reset */

		resets = <&gcc GCC_SDCC1_BCR>;

		reset-names = "core_reset";



		status = "disabled";



		qos0 {
@@ -2616,6 +2626,10 @@ 
		reg = <0x08804000 0x1000>;

		reg-names = "hc_mem";



		iommus = <&apps_smmu 0x100 0x0>;

		dma-coherent;

		qcom,iommu-dma = "bypass";



		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";