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Commit 9ba1baac authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: clk-rcg2: Fix QUPV3 DFSR M and N register mode overwrite"

parents a4a89a61 3934ca8e

drivers/clk/qcom/clk-rcg.h

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_RCG_H__

#define __QCOM_CLK_RCG_H__
@@ -179,7 +179,7 @@ struct clk_rcg_dfs_data { 
};



#define DEFINE_RCG_DFS(r) \

	{ .rcg = &r##_src, .init = &r##_init }

	{ .rcg = &r, .init = &r##_init }



extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,

				    const struct clk_rcg_dfs_data *rcgs,

drivers/clk/qcom/clk-rcg2.c

+4 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -1243,6 +1243,9 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 
	if (cfg & mask)

		f->pre_div = cfg & mask;



	mode = cfg & CFG_MODE_MASK;

	mode >>= CFG_MODE_SHIFT;



	cfg &= CFG_SRC_SEL_MASK;

	cfg >>= CFG_SRC_SEL_SHIFT;
@@ -1255,8 +1258,6 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 
		}

	}



	mode = cfg & CFG_MODE_MASK;

	mode >>= CFG_MODE_SHIFT;

	if (mode) {

		mask = BIT(rcg->mnd_width) - 1;

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),