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Commit 3934ca8e authored by Vivek Aknurwar's avatar Vivek Aknurwar Committed by David Collins
Browse files

clk: qcom: clk-rcg2: Fix QUPV3 DFSR M and N register mode overwrite 



Move reading of MN counter mode register earlier to source sel
to fix overwrite of MN counter mode variable.

Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 6d960dcc

drivers/clk/qcom/clk-rcg2.c

+4 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -1243,6 +1243,9 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 
	if (cfg & mask)

		f->pre_div = cfg & mask;



	mode = cfg & CFG_MODE_MASK;

	mode >>= CFG_MODE_SHIFT;



	cfg &= CFG_SRC_SEL_MASK;

	cfg >>= CFG_SRC_SEL_SHIFT;
@@ -1255,8 +1258,6 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 
		}

	}



	mode = cfg & CFG_MODE_MASK;

	mode >>= CFG_MODE_SHIFT;

	if (mode) {

		mask = BIT(rcg->mnd_width) - 1;

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),