scsi: ufs: Add workaround to bypass cfgready signal for UFS gear4

The tx_cfg_rdy signal from PHY to Controller to indicate
EOB(END OF BURST) runs using TX CFG clock which is half the Uniproclk
freq. But it is observed that tx_cfg_rdyn signal is getting sampled in
controller using Uniproclk (300 MHz) instead of TX CFG clock (150 MHz)
and hence FSM in controller is going into unwanted state when only
one of tx_cfg_rdyn_0 and tx_cfg_rdyn_1 is 0 around sampling clock edge.

To workaround this issue, control should bypass the Cfgready
signal(TX_CFGREADY and RX_CFGREDY) because controller stills wait
for another signal tx_savestatusn which will serve same purpose.

Change-Id: I2f32542682571ba6e7b1266393dfb1168dc68658
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>