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Commit 9401273d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Enable 747MHz GPU Fmax for Shima"

parents 2362bf12 09a68ad8

qcom/shima-gpu.dtsi

+48 −20
Original line number Diff line number Diff line
@@ -143,10 +143,24 @@ 
				#size-cells = <0>;



				qcom,speed-bin = <0>;

				qcom,initial-pwrlevel = <4>;

				qcom,initial-pwrlevel = <5>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <747000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



					qcom,bus-freq-ddr7 = <11>;

					qcom,bus-min-ddr7 = <11>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <11>;

					qcom,bus-min-ddr8 = <10>;

					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <676000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -154,13 +168,13 @@ 
					qcom,bus-min-ddr7 = <10>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <11>;

					qcom,bus-freq-ddr8 = <10>;

					qcom,bus-min-ddr8 = <9>;

					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@1 {

					reg = <1>;

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <608000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -173,8 +187,8 @@ 
					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@2 {

					reg = <2>;

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <540000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -187,8 +201,8 @@ 
					qcom,bus-max-ddr8 = <10>;

				};



				qcom,gpu-pwrlevel@3 {

					reg = <3>;

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <443000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -201,8 +215,8 @@ 
					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@4 {

					reg = <4>;

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <285000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -307,10 +321,24 @@ 
				#size-cells = <0>;



				qcom,speed-bin = <158>;

				qcom,initial-pwrlevel = <4>;

				qcom,initial-pwrlevel = <5>;



				qcom,gpu-pwrlevel@0 {

					reg = <0>;

					qcom,gpu-freq = <747000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



					qcom,bus-freq-ddr7 = <11>;

					qcom,bus-min-ddr7 = <11>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <11>;

					qcom,bus-min-ddr8 = <10>;

					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@1 {

					reg = <1>;

					qcom,gpu-freq = <676000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -318,13 +346,13 @@ 
					qcom,bus-min-ddr7 = <10>;

					qcom,bus-max-ddr7 = <11>;



					qcom,bus-freq-ddr8 = <11>;

					qcom,bus-freq-ddr8 = <10>;

					qcom,bus-min-ddr8 = <9>;

					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@1 {

					reg = <1>;

				qcom,gpu-pwrlevel@2 {

					reg = <2>;

					qcom,gpu-freq = <608000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -337,8 +365,8 @@ 
					qcom,bus-max-ddr8 = <11>;

				};



				qcom,gpu-pwrlevel@2 {

					reg = <2>;

				qcom,gpu-pwrlevel@3 {

					reg = <3>;

					qcom,gpu-freq = <540000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -351,8 +379,8 @@ 
					qcom,bus-max-ddr8 = <10>;

				};



				qcom,gpu-pwrlevel@3 {

					reg = <3>;

				qcom,gpu-pwrlevel@4 {

					reg = <4>;

					qcom,gpu-freq = <443000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -365,8 +393,8 @@ 
					qcom,bus-max-ddr8 = <9>;

				};



				qcom,gpu-pwrlevel@4 {

					reg = <4>;

				qcom,gpu-pwrlevel@5 {

					reg = <5>;

					qcom,gpu-freq = <285000000>;

					qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;