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Commit 93f25318 authored by Alex Dai's avatar Alex Dai Committed by Daniel Vetter
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drm/i915/guc: Media domain bit needed when notify GuC rc6 state 



GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.

v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating

v1: Add parameters definition to avoid magic value

Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 36c0d0cf

drivers/gpu/drm/i915/i915_guc_submission.c

+11 −2
Original line number Diff line number Diff line
@@ -155,12 +155,21 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, 
				     struct i915_guc_client *client)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct drm_device *dev = dev_priv->dev;

	u32 data[2];



	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;

	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;

	/* WaRsDisableCoarsePowerGating:skl,bxt */

	if (!intel_enable_rc6(dev_priv->dev) ||

	    (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||

	    (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) ||

	    (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))

		data[1] = 0;

	else

		/* bit 0 and 1 are for Render and Media domain separately */

		data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;



	return host2guc_action(guc, data, 2);

	return host2guc_action(guc, data, ARRAY_SIZE(data));

}



/*

drivers/gpu/drm/i915/intel_guc_fwif.h

+3 −0
Original line number Diff line number Diff line
@@ -218,6 +218,9 @@ struct guc_context_desc { 
	u64 desc_private;

} __packed;



#define GUC_FORCEWAKE_RENDER	(1 << 0)

#define GUC_FORCEWAKE_MEDIA	(1 << 1)



/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */

enum host2guc_action {

	HOST2GUC_ACTION_DEFAULT = 0x0,